公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US11314589B2

公开(公告)日：2022-04-26

申请号：US16875642

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US20220094553A1

公开(公告)日：2022-03-24

申请号：US17542842

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

IPC: H04L9/32 ,  G06F3/06 ,  G11C29/52 ,  H04L9/06 ,  G06F11/10 ,  G06F12/0886 ,  G06F12/14 ,  G06F21/79 ,  H04L9/08 ,  G06F21/78

Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

公开(公告)号：US20210263855A1

公开(公告)日：2021-08-26

申请号：US17223113

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

公开(公告)号：US20200185052A1

公开(公告)日：2020-06-11

申请号：US16795119

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit Bains ,  Wei Chen ,  Rajat Agarwal

IPC: G11C29/00 ,  G11C29/44 ,  G11C11/406 ,  G11C7/10

Abstract: An embodiment of an electronic memory apparatus may include storage media, and logic communicatively coupled to the storage media, the logic to determine if a mode is set to one of a first mode or a second mode, perform a soft post package repair in the first mode, and undo the soft post package repair in the second mode. Other embodiments are disclosed and claimed.

公开(公告)号：US20200177392A1

公开(公告)日：2020-06-04

申请号：US16689575

申请日：2019-11-20

Applicant: INTEL CORPORATION

Inventor： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

IPC: H04L9/32 ,  G06F12/14 ,  G06F21/78 ,  G06F11/10 ,  H04L9/06 ,  H04L9/08 ,  G06F21/79 ,  G06F12/0886 ,  G06F3/06 ,  G11C29/52

Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

公开(公告)号：US10409727B2

公开(公告)日：2019-09-10

申请号：US15475249

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Berkin Akin ,  Rajat Agarwal ,  Jong Soo Park ,  Christopher J. Hughes ,  Chiachen Chou

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/04 ,  G06F12/0831 ,  G06F12/0886

Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

公开(公告)号：US20190266087A1

公开(公告)日：2019-08-29

申请号：US16408870

申请日：2019-05-10

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Rajat Agarwal

IPC: G06F12/0811 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1009

Abstract: A processor includes a core to execute a transaction with a memory via cache; and cache controller having an index mapper circuit to: identify a physical memory address associated with the transaction and having a plurality of bits; determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value; determine a mapping function corresponding to the tag value; determine, using the mapping function, a bit-placement order; combine, based on the order, second and third set of bits to form an index; generate, using the index, a mapping from the address to a cache line index value identifying a cache line in the cache; and wherein the cache controller is further to access, using the mapping and in response to the transaction, the cache line.

公开(公告)号：US20190229924A1

公开(公告)日：2019-07-25

申请号：US16368810

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Rajat Agarwal ,  David M. Durham

IPC: H04L9/32 ,  H04L29/06 ,  H04L9/16 ,  H04L9/08 ,  H04L9/06 ,  H04L9/00

Abstract: In one example a computer implemented method comprises encrypting data to be stored in a protected region of a memory using a message authentication code (MAC) having a first value determined using a first key during a first period of time, generating a replay integrity tree structure comprising security metadata for the data stored in the protected region of the memory using the first value of the MAC, and at the end of the first period of time, re-keying the MAC to have a second value determined using a second key at the end of the first period of time, decrypting the data stored in the protected region using the first value for the MAC, re-encrypting the data stored in the protected region using the second value for the MAC, and updating the replay integrity tree using the second value for the MAC. Other examples may be described.

公开(公告)号：US20190044973A1

公开(公告)日：2019-02-07

申请号：US16023941

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  David Durham ,  Karanvir Grewal ,  Rajat Agarwal

IPC: H04L29/06 ,  H04L9/08 ,  H04L9/14

Abstract: The present disclosure is directed to systems and methods for providing protection against replay attacks on memory, by refreshing or updating encryption keys. The disclosed replay protected computing system may employ encryption refresh of memory so that unauthorized copies of data are usable for a limited amount of time (e.g., 500 milliseconds or less). The replay protected computing system initially encrypts protected data prior to storage in memory. After a predetermined time or after a number of memory accesses have occurred, the replay protected computing system decrypts the data with the existing key and re-encrypts data with a new key. Unauthorized copies of data (such as those made by an adversary system/program) are not refreshed with subsequent new keys. When an adversary program attempts to use the unauthorized copies of data, the unauthorized copies of data are decrypted with the incorrect keys, which renders the decrypted data unintelligible.