公开(公告)号：US10734513B2

公开(公告)日：2020-08-04

申请号：US15768822

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Jack T. Kavalieros ,  Elijah V. Karpov ,  Uday Shah ,  Ravi Pillarisetty

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/267

Abstract: Heterojunction tunnel field effect transistors (hTFETs) incorporating one or more oxide semiconductor and a band offset between at least one of a channel material, a source material of a first conductivity type, and drain of a second conductivity type, complementary to the first. In some embodiments, at least one of p-type material, channel material and n-type material comprises an oxide semiconductor. In some embodiments, two or more of p-type material, channel material, and n-type material comprises an oxide semiconductor. In some n-type hTFET embodiments, all of p-type, channel, and n-type materials are oxide semiconductors with a type-II or type-III band offset between the p-type and channel material.

公开(公告)号：US20200235244A1

公开(公告)日：2020-07-23

申请号：US16650793

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Abhishek Sharma ,  Elijah Karpov ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: H01L29/78 ,  H01L29/66

Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.

公开(公告)号：US20200235163A1

公开(公告)日：2020-07-23

申请号：US16630924

申请日：2017-09-14

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Abhishek A. Sharma

IPC: H01L27/24 ,  H01L27/22

Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur.

公开(公告)号：US10706921B2

公开(公告)日：2020-07-07

申请号：US16080922

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Elijah V. Karpov ,  Ravi Pillarisetty ,  Prashant Majhi ,  Niloy Mukherjee ,  Uday Shah

IPC: G11C13/00 ,  H01L27/24

Abstract: One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.

公开(公告)号：US10686007B2

公开(公告)日：2020-06-16

申请号：US16012815

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L27/18 ,  H01L39/22 ,  H01L49/02 ,  G06N10/00 ,  H01L39/02 ,  H01L39/24 ,  H03K19/195

Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

公开(公告)号：US10665770B2

公开(公告)日：2020-05-26

申请号：US15913799

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Kanwaljit Singh ,  Patrick H. Keys ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  James S. Clarke ,  Roza Kotlyar ,  Payam Amin ,  Jeanette M. Roberts

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/24 ,  H01L39/04 ,  G06N10/00 ,  H01L29/12 ,  H01L27/18 ,  H01L29/66 ,  B82Y10/00 ,  H01L39/14 ,  H01L29/76 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L21/8234

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

公开(公告)号：US10665769B2

公开(公告)日：2020-05-26

申请号：US16011829

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L39/02 ,  H01L27/18 ,  H01L39/24 ,  H01L39/04 ,  G06N10/00 ,  H01L39/22

Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.

公开(公告)号：US10573809B2

公开(公告)日：2020-02-25

申请号：US16077571

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Pulkit Jain ,  Aravind S. Killampalli ,  Jay P. Gupta ,  James S. Clarke

IPC: H01L45/00

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

公开(公告)号：US20200020805A1

公开(公告)日：2020-01-16

申请号：US16490502

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: Disclosed are systems, methods, and apparatus directed to the fabrication of vertical field effect transistors (VFETs) and VFETs with self-aligned wordlines. In one embodiment, the source and/or drain of the VFETs can include n-doped silicon. In one embodiment, the VFETs can include a channel that can be made of intrinsic silicon. In one embodiment, the source, drain, and/or channel can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD), and the like. In one embodiment, an STI process can be used to fabricate one or more recesses, which can reach the drains of the VFETs. In one embodiment, the systems, methods, and apparatus can permit the self-alignment of one or more wordlines of the VFETs with the one or more fins, and/or gate metals and gate materials of the VFETs.

公开(公告)号：US20190392352A1

公开(公告)日：2019-12-26

申请号：US16016840

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: G06N99/00 ,  G06F15/18 ,  G06F17/18 ,  G06F1/20

Abstract: Embodiments of the present disclosure provide quantum circuit assemblies that implement adaptive programming of quantum dot qubit devices. An example quantum circuit assembly includes a quantum circuit component including a quantum dot qubit device, and a control logic coupled to the quantum circuit component. The control logic is configured to adaptively program the quantum dot qubit device by iterating a sequence of applying one or more signals to the quantum dot qubit device, determining a state of at least one qubit of the quantum dot qubit device, and using the determined state to modify the signals to be applied to the quantum dot qubit device in the next iteration. In this manner, the signals may be fine-tuned to achieve a higher probability of the qubit(s) in the quantum dot qubit device being set to the desired state.