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公开(公告)号：US20230315143A1
公开(公告)日：2023-10-05
申请号：US18329492
申请日：2023-06-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F9/30 , G06F9/455 , G06F1/324
CPC classification number: G06F1/08 , G06F1/3203 , G06F9/30101 , G06F9/45558 , G06F1/324 , G06F2009/45591
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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公开(公告)号：US11657561B2
公开(公告)日：2023-05-23
申请号：US17719089
申请日：2022-04-12
Applicant: Intel Corporation
Inventor： Ankur Shah , Matthew Callaway , Vivek Garg , Rajeev K. Nalawadi , James Varga
CPC classification number: G06T15/005 , G06F1/28 , G06F9/45558 , G06F9/4881 , G06F9/5077 , G06F2009/4557
Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta. For example, one embodiment of a graphics processing apparatus comprises virtualization control circuitry to virtualize graphics processing resources of one or more graphics processing units (GPU), wherein one or more virtual machines (VMs) are to be provided with controlled access to the graphics processing resources in accordance with a current graphics virtualization configuration specified, at least in part, in one or more virtualization control registers of the virtualization control circuitry; a scheduler to schedule each VM for processing by the graphics processing resources in accordance with the graphics virtualization configuration, the scheduler to generate a VM switch event responsive to each VM being scheduled for processing on the graphics processing resources; power management circuitry to collect telemetry data associated with VMs which have temporarily completed processing on the graphics processing resources and to forward the telemetry data to a telemetry data aggregator, the telemetry data aggregator to combine telemetry data collected for each VM over a period of time and to store per-VM telemetry data in a data repository accessible by a virtualization management application.
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公开(公告)号：US11237614B2
公开(公告)日：2022-02-01
申请号：US16454378
申请日：2019-06-27
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
IPC: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3234 , G06F1/3296 , G06F1/3225
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
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公开(公告)号：US10474208B2
公开(公告)日：2019-11-12
申请号：US15086456
申请日：2016-03-31
Applicant: INTEL CORPORATION
Inventor： Daniel G. Cartagena , Corey D. Gough , Vivek Garg , Nikhil Gupta
IPC: G06F1/20 , G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3296
Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.
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Patent Agency Ranking
公开(公告)号：US20190102221A1
公开(公告)日：2019-04-04
申请号：US15720296
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Vijay Dhanraj , Russell J. Fenger , Vivek Garg , Eugene Gorbatov , Stephen H. Gunter , Monica Gupta , Efraim Rotem , Krishnakanth V. Sistla , Guy M. Therien , Ankush Varma , Eliezer Weissmann
Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.
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公开(公告)号：US10048744B2
公开(公告)日：2018-08-14
申请号：US14554384
申请日：2014-11-26
Applicant: Intel Corporation
Inventor： Tessil Thomas , Phani Kumar Kandula , Ramamurthy Krithivas , Howard Chin , Ian M. Steiner , Vivek Garg
Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.
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公开(公告)号：US09471118B2
公开(公告)日：2016-10-18
申请号：US14195737
申请日：2014-03-03
Applicant: INTEL CORPORATION
Inventor： Deep Buch , Vivek Garg , Subramaniam Maiyuran
CPC classification number: G06F1/206 , G06F1/3287
Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
Abstract translation: 描述了一种方法，其涉及通过一个无孔部来控制交通等级，以提供对该无孔的热管理。 所述方法包括确定第一非核状态中的非空气温度是否高于第一阈值，并且如果所述非空温度高于所述第一阈值，则将所述第一非空状态改变为第二非空状态。
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公开(公告)号：US20160170468A1
公开(公告)日：2016-06-16
申请号：US15048189
申请日：2016-02-19
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/3243 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
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公开(公告)号：US09235244B2
公开(公告)日：2016-01-12
申请号：US13785259
申请日：2013-03-05
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/3243 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，多核处理器包括可独立执行指令的核心，每个指令以独立的电压和频率进行。 处理器可以包括具有用于提供处理器的电源管理特征的可配置性的逻辑的功率控制器。 一种这样的特征使得至少一个核可以基于存在于控制寄存器中的单个功率域指示符的状态在独立的性能状态下操作。 描述和要求保护其他实施例。
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