公开(公告)号：US20240006315A1

公开(公告)日：2024-01-04

申请号：US17854305

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  REINALDO VEGA ,  David Wolpert ,  Kisik Choi

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/498 ,  H01L21/8238 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L23/49822 ,  H01L21/823871 ,  H01L21/76898

Abstract: A semiconductor array structure includes a substrate; a plurality of field effect transistors (FETs) arranged in rows and located on the substrate, each comprising a first source-drain region, a second source-drain region, at least one channel coupling the source-drain regions, and a gate adjacent the at least one channel. A plurality of frontside signal lines are on a front side of the FETs; a plurality of backside power rails are on a back side of the FETs; a plurality of backside signal wires are on the back side. Frontside signal connections run from the frontside signal lines to the first source-drain regions; Power connections run from the backside power rails to the second source-drain regions; and backside gate contact connections run from the backside signal wires to the gates. The backside gate contact connections each have a bottom dimension larger than the gate length.

公开(公告)号：US20230422461A1

公开(公告)日：2023-12-28

申请号：US17808178

申请日：2022-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： REINALDO VEGA ,  Takashi Ando ,  Praneet Adusumilli ,  David Wolpert ,  Cheng Chi

IPC: H01L27/11 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L27/1104 ,  H01L23/5286 ,  H01L28/40

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

公开(公告)号：US11830778B2

公开(公告)日：2023-11-28

申请号：US17095931

申请日：2020-11-12

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Daniel James Dechene ,  Lawrence A. Clevenger ,  Michael Romain ,  Somnath Ghosh

IPC: H01L21/66 ,  H01L23/14 ,  H01L21/67 ,  H01L23/13

CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67288 ,  H01L23/13 ,  H01L23/14

Abstract: A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.

公开(公告)号：US11822867B2

公开(公告)日：2023-11-21

申请号：US17401441

申请日：2021-08-13

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Michael Stewart Gray ,  Mitchell R. DeHond

IPC: G06F30/398 ,  G06F115/12 ,  G06F113/18 ,  G06F111/04

CPC classification number: G06F30/398 ,  G06F2111/04 ,  G06F2113/18 ,  G06F2115/12

Abstract: Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

公开(公告)号：US20230062945A1

公开(公告)日：2023-03-02

申请号：US17411113

申请日：2021-08-25

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Ryan Michael Kruse ,  Leon Sigal ,  Richard Edward Serton ,  Matthew Stephen Angyal ,  Terence Hook ,  Richard Andre Wachnik

IPC: G06F30/394 ,  H01L27/02

Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

公开(公告)号：US11586798B1

公开(公告)日：2023-02-21

申请号：US17401379

申请日：2021-08-13

Applicant: International Business Machines Corporation

Inventor： Brian Veraa ,  David Wolpert ,  Ryan Michael Kruse ,  Christopher Gonzalez

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/343 ,  G06F30/347 ,  G06F117/10 ,  G06F119/06

Abstract: A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.

公开(公告)号：US11487308B2

公开(公告)日：2022-11-01

申请号：US16573347

申请日：2019-09-17

Applicant: International Business Machines Corporation

Inventor： Haard Kamlesh Mehta ,  David Wolpert

IPC: G05D23/19 ,  G05F1/46 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06N20/00 ,  G06F1/20 ,  G06F11/34

Abstract: A system, method and computer program product for operating a low-voltage Internet-of-Things sensor device. The method includes sensing of the temperature dependence at each voltage condition in addition to the actual temperature and voltage. A programmed machine learning model uses the information to decide when it is appropriate to test the device functionality and use the results of different tests to determine when the system should run synchronously or asynchronously through a machine learning predictive algorithm. Based on said one or more sensed operating conditions, the system uses the model to detect a mode of operation of said IoT device indicating IoT device meets an expected level of performance, or a mode indicating said IoT device is not operating according to the expected level of performance. Based on the detected operating condition, the IoT device automatically adapts its operation to ensure a desired level of IoT sensor device performance.

公开(公告)号：US10503864B1

公开(公告)日：2019-12-10

申请号：US16009605

申请日：2018-06-15

Applicant: International Business Machines Corporation

Inventor： Alan P. Wagstaff ,  David Wolpert

IPC: G06F17/50

Abstract: Using unused wires on VLSI chips for power supply decoupling including generating a VLSI chip design by: identifying floating wires in a VLSI chip; placing a via at each intersection between each floating wire and a power rail; determining a number of design rule violations for each via at each intersection; resolving the design rule violations for each via not on a major power rail; resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail; after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via; and for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.

公开(公告)号：US20250169131A1

公开(公告)日：2025-05-22

申请号：US18515560

申请日：2023-11-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  David Wolpert ,  Brent A. Anderson ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Lawrence A. Clevenger

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor structure includes a substrate, one or more nanosheet channel layers disposed over the substrate, and a dielectric bar attached to the one or more nanosheet channel layers, where the dielectric bar is not perpendicular to the substrate. The one or more nanosheet channel layers include a first set of one or more nanosheet channels attached to a first side of the dielectric bar and a second set of one or more nanosheet channels attached to a second side of the dielectric bar.

公开(公告)号：US20250048695A1

公开(公告)日：2025-02-06

申请号：US18365989

申请日：2023-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  James P. Mazza ,  Nicholas Anthony Lanzillo ,  David Wolpert

IPC: H01L29/08 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate and a plurality of stacked transistors positioned on the substrate. The transistors include a gate region and a source and drain proximate the gate region. The source and drain includes an overall region and an active region. A thickness of the active region is less than a thickness of the overall region.