公开(公告)号：US20150044853A1

公开(公告)日：2015-02-12

申请号：US14521743

申请日：2014-10-23

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/84 ,  H01L27/10847 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/945

Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Abstract translation: 在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。 电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。 ％至20重量％ ％。

公开(公告)号：US20150021699A1

公开(公告)日：2015-01-22

申请号：US13945095

申请日：2013-07-18

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/0886 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4908

Abstract: A high dielectric constant (high-k) gate dielectric layer is formed on semiconductor fins including one or more semiconductor materials. A patterned diffusion barrier metallic nitride layer is formed to overlie at least one channel, while not overlying at least another channel. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one workfunction material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks straddling the semiconductor fins.

Abstract translation: 在包括一种或多种半导体材料的半导体鳍片上形成高介电常数（高k）栅极电介质层。 形成图案化扩散阻挡金属氮化物层以覆盖至少一个通道，而不覆盖至少另一个通道。 在高k栅极电介质层和扩散阻挡金属氮化物层的物理暴露部分上形成阈值电压调整氧化物层。 执行退火以将阈值电压调节氧化物层的材料驱动到本征通道和高k栅极电介质层之间的界面，从而形成阈值电压调节氧化物部分。 形成至少一个功函数材料层，并用高k栅极介电层和阈值电压调整氧化物部分进行图案化以形成跨越半导体鳍片的多种类型的栅叠层。

公开(公告)号：US20140262803A1

公开(公告)日：2014-09-18

申请号：US13800201

申请日：2013-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shafaat Ahmed ,  Michael P. Chudzik ,  Lubomyr T. Romankiw

IPC: C25D5/20 ,  C25D7/12

CPC classification number: C25D21/04 ,  C25D5/04 ,  C25D5/08 ,  C25D5/20 ,  C25D7/123 ,  C25D17/001 ,  C25D17/008 ,  C25D21/10

Abstract: An electroplating apparatus includes an anode configured to electrically communicate with an electrical voltage and an electrolyte solution. A cathode module includes a cathode that is configured to electrically communicate with a ground potential and the electrolyte solution. The cathode module further includes a wafer in electrical communication with the cathode. The wafer is configured to receive metal ions from the anode in response to current flowing through the anode via electrodeposition. The electroplating apparatus further includes at least one agitating device interposed between the wafer and the anode. The agitating device is configured to apply a force to gas bubbles adhering to a surface of the wafer facing the agitating device.

Abstract translation: 电镀设备包括被配置为与电压和电解质溶液电连通的阳极。 阴极模块包括被配置为与地电位和电解质溶液电连通的阴极。 阴极模块还包括与阴极电连通的晶片。 晶片被配置为响应于电流通过电沉积而流过阳极而从阳极接收金属离子。 电镀装置还包括插入在晶片和阳极之间的至少一个搅拌装置。 搅拌装置构造成对粘附到面向搅拌装置的晶片表面的气泡施加力。

公开(公告)号：US08836048B2

公开(公告)日：2014-09-16

申请号：US13653679

申请日：2012-10-17

Applicant: International Business Machines Corporation

Inventor： Cyril Cabral, Jr. ,  Josephine B. Chang ,  Michael P. Chudzik ,  Martin M. Frank ,  Michael A. Guillorn ,  Christian Lavoie ,  Shreesh Narasimha ,  Vijay Narayanan

IPC: H01L21/70

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66507 ,  H01L29/6659

Abstract: A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure.

Abstract translation: 一种半导体器件，包括存在于半导体衬底的沟道部分上的栅极结构和邻近栅极结构的至少一个栅极侧壁间隔物。 在一个实施例中，栅极结构包括存在于栅极电介质层上的功函数金属层，存在于功函数金属层上的金属半导体合金层和存在于金属半导体合金层上的电介质覆盖层。 所述至少一个栅极侧壁间隔物和介电覆盖层可以将栅极结构内的金属半导体合金层封装。

公开(公告)号：US20140225199A1

公开(公告)日：2014-08-14

申请号：US14254939

申请日：2014-04-17

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Martin M. Frank ,  Herbert L. Ho ,  Mark J. Hurley ,  Rashmi Jha ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

IPC: H01L29/49 ,  H01L27/092

CPC classification number: H01L29/49 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/517

Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Abstract translation: 提出了离子注入来改变双功能金属栅极整合的有效功函数。 一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

公开(公告)号：US20140103457A1

公开(公告)日：2014-04-17

申请号：US13653679

申请日：2012-10-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cyril Cabral, JR. ,  Josephine B. Chang ,  Michael P. Chudzik ,  Martin M. Frank ,  Michael A. Guillorn ,  Christian Lavoie ,  Shreesh Narasimha ,  Vijay Narayanan

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66507 ,  H01L29/6659

Abstract: A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure.

公开(公告)号：US20170170077A1

公开(公告)日：2017-06-15

申请号：US14967914

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Min Dai ,  Dominic J. Schepis ,  Shahab Siddiqui

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

公开(公告)号：US09673108B1

公开(公告)日：2017-06-06

申请号：US14967914

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Min Dai ,  Dominic J. Schepis ,  Shahab Siddiqui

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

公开(公告)号：US20150349076A1

公开(公告)日：2015-12-03

申请号：US14826466

申请日：2015-08-14

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/423 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

Abstract translation: 形成半导体器件的方法包括在半导体衬底上形成第一和第二半导体结构。 第一半导体结构包括具有第一栅极长度的第一栅极沟道区，并且第二半导体结构包括具有大于第一栅极长度的第二栅极长度的第二栅极沟道区。 该方法还包括在第一栅极沟道区域中形成的第一栅极空隙和形成在第二栅极沟道区域处的第二栅极空穴中沉积功函数金属层。 该方法还包括在功函数金属层上沉积半导体掩模层，同时蚀刻位于第一和第二栅极沟道区的硅掩模层，以重新暴露第一和第二栅极空隙。 在第一和第二栅极空隙中沉积低电阻金属以形成低电阻金属栅极叠层。

公开(公告)号：US09099394B2

公开(公告)日：2015-08-04

申请号：US14066119

申请日：2013-10-29

Applicant: International Business Machines Corporation

Inventor： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L27/112 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L27/115 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49

CPC classification number: H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

Abstract translation: 在半导体衬底上同时形成用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和非易失性随机存取存储器（NVRAM）器件的高k隧道电介质。 随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。 沉积并图案化平坦化介电层，并且去除一次性材料部分。 控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。 导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。 或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。