-
1.发明申请公开(公告)号：US20170154825A1
公开(公告)日：2017-06-01
申请号：US15290410
申请日：2016-10-11
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/12 , H01L21/84 , H01L27/092 , H01L29/49
CPC分类号： H01L21/823842 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66545 , H01L29/785 , H01L29/786
摘要： An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
-
公开(公告)号：US20160276216A1
公开(公告)日：2016-09-22
申请号：US15151260
申请日：2016-05-10
发明人： DANIEL EDELSTEIN , Alfred Grill , Seth L. Knupp , Son Nguyen , Takeshi Nogami , Vamsi K. Paruchuri , Hosadurga K. Shobha , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , C23C16/30 , C23C16/56 , C23C16/455 , H01L23/522 , C23C16/06
CPC分类号： H01L21/76843 , C23C16/04 , C23C16/06 , C23C16/16 , C23C16/18 , C23C16/30 , C23C16/45525 , C23C16/45544 , C23C16/505 , C23C16/54 , C23C16/56 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L21/76852 , H01L21/76862 , H01L21/76864 , H01L21/76879 , H01L21/76883 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.
-
公开(公告)号：US08980715B2
公开(公告)日：2015-03-17
申请号：US14012448
申请日：2013-08-28
发明人： Alfred Grill , Seth L. Knupp , Son V. Nguyen , Vamsi K. Paruchuri , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L29/78 , H01L23/532 , H01L21/02 , H01L29/66
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02247 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/76283 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/481 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
摘要翻译： 提供具有氮化硅（SiN）和氮氧化硅（SiNO）膜用作封盖层，衬垫，间隔壁和蚀刻停止层以及半导体纳米器件的其它部件的多层电介质结构。 例如，半导体结构包括具有包括一个或多个SiN层和一个或多个SiNO层的多层电介质材料的多层电介质结构。 多层电介质结构中的介电材料层的厚度在约0.5纳米至约3纳米的范围内。
-
公开(公告)号：US20140256153A1
公开(公告)日：2014-09-11
申请号：US14012448
申请日：2013-08-28
发明人： Alfred Grill , Seth L. Knupp , Son V. Nguyen , Vamsi K. Paruchuri , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L21/02
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02247 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/76283 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/481 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
摘要翻译： 提供具有氮化硅（SiN）和氮氧化硅（SiNO）膜用作封盖层，衬垫，间隔壁和蚀刻停止层以及半导体纳米器件的其它部件的多层电介质结构。 例如，半导体结构包括具有包括一个或多个SiN层和一个或多个SiNO层的多层电介质材料的多层电介质结构。 多层电介质结构中的介电材料层的厚度在约0.5纳米至约3纳米的范围内。
-
公开(公告)号：US20170256498A1
公开(公告)日：2017-09-07
申请号：US15603831
申请日：2017-05-24
IPC分类号： H01L23/532 , H01L23/528 , H01L21/02 , H01L21/3213 , H01L21/768 , H01L21/288
CPC分类号： H01L23/53238 , H01L21/02164 , H01L21/288 , H01L21/2885 , H01L21/32133 , H01L21/76834 , H01L21/76846 , H01L21/7685 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76885 , H01L21/76886 , H01L23/528
摘要： A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.
-
公开(公告)号：US09721893B2
公开(公告)日：2017-08-01
申请号：US15153110
申请日：2016-05-12
IPC分类号： H01L21/76 , H01L23/532 , H01L21/768 , H01L21/02 , H01L21/288 , H01L21/3213 , H01L23/528
CPC分类号： H01L23/53238 , H01L21/02164 , H01L21/288 , H01L21/2885 , H01L21/32133 , H01L21/76834 , H01L21/76846 , H01L21/7685 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76885 , H01L21/76886 , H01L23/528
摘要： A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.
-
公开(公告)号：US20150311127A1
公开(公告)日：2015-10-29
申请号：US14739627
申请日：2015-06-15
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/225 , H01L29/40 , H01L29/423
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。
-
8.发明申请CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION 有权在双功能金属门整合期间使用离子植入改变有效的工作功能公开(公告)号：US20140225199A1
公开(公告)日：2014-08-14
申请号：US14254939
申请日：2014-04-17
发明人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L29/49 , H01L27/092
CPC分类号： H01L29/49 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/517
摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
摘要翻译： 提出了离子注入来改变双功能金属栅极整合的有效功函数。 一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。
-
公开(公告)号：US11177167B2
公开(公告)日：2021-11-16
申请号：US15150961
申请日：2016-05-10
发明人： Daniel Edelstein , Alfred Grill , Seth L. Knupp , Son Nguyen , Takeshi Nogami , Vamsi K. Paruchuri , Hosadurga K. Shobha , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/285 , C23C16/18 , C23C16/16 , C23C16/06 , C23C16/30 , C23C16/56 , H01L23/522 , H01L23/528 , C23C16/455 , C23C16/54 , C23C16/04 , C23C16/505
摘要： Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.
-
公开(公告)号：US10008449B2
公开(公告)日：2018-06-26
申请号：US15603831
申请日：2017-05-24
IPC分类号： H01L23/52 , H01L21/76 , H01L23/532 , H01L21/768 , H01L23/528 , H01L21/288 , H01L21/02 , H01L21/3213
CPC分类号： H01L23/53238 , H01L21/02164 , H01L21/288 , H01L21/2885 , H01L21/32133 , H01L21/76834 , H01L21/76846 , H01L21/7685 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76885 , H01L21/76886 , H01L23/528
摘要： A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.021 秒)
