公开(公告)号：US20170250073A1

公开(公告)日：2017-08-31

申请号：US15595503

申请日：2017-05-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L21/02 ,  H01L21/20 ,  H01G4/005 ,  H01L21/322

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

公开(公告)号：US09653534B2

公开(公告)日：2017-05-16

申请号：US14572974

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L29/66 ,  H01L49/02 ,  H01L27/108 ,  H01L23/26

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

公开(公告)号：US20160093720A1

公开(公告)日：2016-03-31

申请号：US14499356

申请日：2014-09-29

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Brian J. Greene ,  Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Renee T. Mo ,  Yinxiao Yang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L29/7848

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract translation: 一种用于制造半导体结构的方法以及半导体结构，其使用半导体鳍周围的绝缘层的部分去除，并且随后在暴露区域中外延生长另外的半导体材料，同时保持鳍的形状，同时保持鳍的形状 绝缘层。

公开(公告)号：US20150364603A1

公开(公告)日：2015-12-17

申请号：US14305543

申请日：2014-06-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Kern Rim ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract translation: 一种半导体器件，包括至少一个包含硅的悬浮沟道结构，以及存在于悬挂沟道结构上的栅极结构。 至少一个栅极电介质层存在于悬置沟道结构周围，并且至少一个栅极导体存在于至少一个栅极电介质层上。 源极和漏极结构可以由包括硅和锗的材料组成。 源极和漏极结构通过硅包覆层与悬浮沟道结构的源极和漏极端部接触。

公开(公告)号：US09087784B2

公开(公告)日：2015-07-21

申请号：US14167532

申请日：2014-01-29

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.

Abstract translation: 提供包括缩放的n沟道场效应晶体管（nFET）和缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分来提供这种结构。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以等离子体氮化。 等离子体氮化nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质。

公开(公告)号：US09059313B2

公开(公告)日：2015-06-16

申请号：US13770552

申请日：2013-02-19

Applicant: International Business Machines Corporation

Inventor： Keith Kwong Hon Wong ,  Michael P. Chudzik ,  Unoh Kwon

IPC: H01L21/8238 ,  H01L29/51 ,  H01L29/165 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Abstract translation: 提供了替代栅极堆叠，这增加了p型场效应晶体管（PFET）的栅电极的功函数。 在一个实施例中，功函数金属堆叠包括位于下部氮化钛层和上部氮化钛层之间的氧化钛 - 氮化物层。 下部氮化钛层，钛氧化物 - 氮化物层和上部氮化钛层的堆叠产生显着增加功函数金属叠层功函数的意想不到的结果。 在另一个实施例中，功函数金属堆叠包括在不高于420℃的温度下沉积的铝层。在不高于420℃的温度下沉积的铝层产生增加工件功函数的意想不到的结果 功能金属堆叠显着。

公开(公告)号：US08952460B2

公开(公告)日：2015-02-10

申请号：US14077918

申请日：2013-11-12

Applicant: International Business Machines Corporation

Inventor： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

IPC: H01L21/70 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/518 ,  H01L21/28255 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract translation: 一种半导体器件，包括在所述半导体衬底的沟道区上包括栅极结构的含锗衬底。 栅极结构可以包括与含锗衬底的上表面直接接触的氧化硅层，与氧化硅层直接接触的至少一个高k栅介质层和直接与锗氧化物层直接接触的至少一个栅极导体 与高k栅介质层接触。 氧化硅层和含锗衬底的上表面之间的界面基本上不含氧化锗。 源极区域和漏极区域可以存在于沟道区域的相对侧上。

公开(公告)号：US08809176B2

公开(公告)日：2014-08-19

申请号：US13842217

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/3205

CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

公开(公告)号：US20140065783A1

公开(公告)日：2014-03-06

申请号：US14073159

申请日：2013-11-06

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Deleep R. Nair ,  Vijay Narayanan ,  Carl J. Radens ,  Jay M. Shah

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L29/66575 ,  H01L21/28017 ,  H01L21/283 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78

Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

Abstract translation: 包括清除材料和电介质材料的至少一层沉积在栅叠层上，随后进行各向异性蚀刻以形成含氧清除材料的栅间隔物。 含氧清除材料的栅极间隔物可以是包含清除纳米颗粒的栅极间隔物或含有扫气岛的栅极间隔物。 清除材料以防止栅极电极和栅极电介质下方的半导体材料之间的电短路的方式分布在含氧清除材料的栅极间隔物内。 清扫材料主动地清除从可以形成在含氧清除材料的栅极间隔物周围形成的介电栅极隔离物的上方或外部扩散到栅极电介质的氧。

公开(公告)号：US20140061819A1

公开(公告)日：2014-03-06

申请号：US14077918

申请日：2013-11-12

Applicant: International Business Machines Corporation

Inventor： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

IPC: H01L29/51 ,  H01L27/092

CPC classification number: H01L29/518 ,  H01L21/28255 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract translation: 一种半导体器件，包括在所述半导体衬底的沟道区上包括栅极结构的含锗衬底。 栅极结构可以包括与含锗衬底的上表面直接接触的氧化硅层，与氧化硅层直接接触的至少一个高k栅介质层和直接与锗氧化物层直接接触的至少一个栅极导体 与高k栅介质层接触。 氧化硅层和含锗衬底的上表面之间的界面基本上不含氧化锗。 源极区域和漏极区域可以存在于沟道区域的相对侧上。