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    Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
    42.
    发明授权
    Host synchronized autonomous data chip address sequencer for a distributed buffer memory system 有权

    公开(公告)号：US10534555B2

    公开(公告)日：2020-01-14

    申请号：US15825909

    申请日：2017-11-29

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Susan M. Eickhoff ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

    IPC: G06F3/06

    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

    Dynamically adjustable cyclic redundancy code types
    43.
    发明授权
    Dynamically adjustable cyclic redundancy code types 有权

    公开(公告)号：US10530396B2

    公开(公告)日：2020-01-07

    申请号：US15817387

    申请日：2017-11-20

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H03M13/00 ,  H03M13/35 ,  H04L1/00 ,  H03M13/09

    Abstract: Aspects of the invention include monitoring frames of bits received at a receiver for transmission errors. At least one of the received frames of bits includes cyclic redundancy code (CRC) bits for a first type of CRC check. It is determined whether a change in transmission errors has occurred in the received frames by performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames. A change from the first type of CRC check to a second type of CRC check is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred. The change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver.

    Host Synchronized Autonomous Data Chip Address Sequencer for A Distributed Buffer Memory System
    45.
    发明申请
    Host Synchronized Autonomous Data Chip Address Sequencer for A Distributed Buffer Memory System 审中-公开

    公开(公告)号：US20190163384A1

    公开(公告)日：2019-05-30

    申请号：US15825909

    申请日：2017-11-29

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Susan M. Eickhoff ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

    IPC: G06F3/06

    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

    Reducing uncorrectable errors based on a history of correctable errors
    47.
    发明授权
    Reducing uncorrectable errors based on a history of correctable errors 有权

    公开(公告)号：US10296417B2

    公开(公告)日：2019-05-21

    申请号：US16043362

    申请日：2018-07-24

    Applicant: International Business Machines Corporation

    Inventor： Glenn D. Gilda ,  Patrick J. Meaney

    IPC: G06F11/10 ,  G11C29/52 ,  G11C29/44 ,  G06F11/00

    Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.

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