公开(公告)号：US20230057992A1

公开(公告)日：2023-02-23

申请号：US17406296

申请日：2021-08-19

申请人： Intel Corporation

发明人： Tanay GOSAVI ,  Raseong KIM ,  Han Wui THEN ,  Ian A. YOUNG

IPC分类号： H01L27/20 ,  H01L29/20 ,  H01L29/778 ,  H03H9/02 ,  H03H9/17 ,  H01L29/66 ,  H03H3/02

摘要： Gallium nitride (GaN) integrated circuit technology with resonators is described. In an example, an integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

公开(公告)号：US20220012581A1

公开(公告)日：2022-01-13

申请号：US17484828

申请日：2021-09-24

申请人： Intel Corporation

发明人： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC分类号： G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10

摘要： An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20200312949A1

公开(公告)日：2020-10-01

申请号：US16368450

申请日：2019-03-28

申请人： Intel Corporation

发明人： Nazila HARATIPOUR ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Owen LOH ,  Mengcheng LU ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Uygar AVCI ,  Jack T. KAVALIEROS

IPC分类号： H01L49/02 ,  H01G4/30 ,  H01G4/012 ,  H01L27/11585 ,  H01L23/522

摘要： A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

公开(公告)号：US20200212291A1

公开(公告)日：2020-07-02

申请号：US16236060

申请日：2018-12-28

申请人： Intel Corporation

发明人： Chia-Ching LIN ,  Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Dmitri NIKONOV ,  Kaan OGUZ ,  Ian A. YOUNG

IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32 ,  H01L27/11 ,  G11C11/16 ,  G11C11/14

摘要： A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.

公开(公告)号：US20200212224A1

公开(公告)日：2020-07-02

申请号：US16232615

申请日：2018-12-26

申请人： Intel Corporation

发明人： Ashish Verma PENUMATCHA ,  Tanay GOSAVI ,  Uygar AVCI ,  Ian A. YOUNG

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  G11C11/22

摘要： Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200118616A1

公开(公告)日：2020-04-16

申请号：US16732951

申请日：2020-01-02

申请人： Intel Corporation

发明人： Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  G11C8/16

摘要： One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US20190243662A1

公开(公告)日：2019-08-08

申请号：US16384715

申请日：2019-04-15

申请人： Intel Corporation

发明人： Vaidyanathan KAUSHIK ,  Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG ,  Tanay KARNIK ,  Huichi LIU

IPC分类号： G06F9/445 ,  G06F1/26 ,  H03K19/0185

CPC分类号： G06F9/445 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/4411 ,  H03K19/018585

摘要： Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20190102170A1

公开(公告)日：2019-04-04

申请号：US16146430

申请日：2018-09-28

申请人： Intel Corporation

发明人： Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ian A. YOUNG

IPC分类号： G06F9/30 ,  G06F9/38 ,  G11C11/419 ,  G11C13/00

摘要： A compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.

公开(公告)号：US20190042160A1

公开(公告)日：2019-02-07

申请号：US16147024

申请日：2018-09-28

申请人： Intel Corporation

发明人： Raghavan KUMAR ,  Phil KNAG ,  Gregory K. CHEN ,  Huseyin Ekin SUMBUL ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC分类号： G06F3/06 ,  G04F10/00 ,  G11C11/419 ,  G11C13/00 ,  G11C11/418

摘要： A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

公开(公告)号：US20180151578A1

公开(公告)日：2018-05-31

申请号：US15576269

申请日：2015-06-26

申请人： INTEL CORPORATION

发明人： Uygar E. AVCI ,  Daniel H. MORRIS ,  Ian A. YOUNG ,  Stephen M. RAMEY

IPC分类号： H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L27/11526 ,  H01L27/02 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/788 ,  H01L29/7881

摘要： Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.