公开(公告)号：US20220093515A1

公开(公告)日：2022-03-24

申请号：US17540079

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US20210305163A1

公开(公告)日：2021-09-30

申请号：US16832150

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US11037802B2

公开(公告)日：2021-06-15

申请号：US16347207

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Sri Ranga Sai Boyapati ,  Sandeep Gaan ,  Srinivas V. Pietambaram

IPC: H01L23/52 ,  H01L21/48 ,  H01L23/498 ,  H05K3/42 ,  H05K3/38

Abstract: Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.

公开(公告)号：US10916486B2

公开(公告)日：2021-02-09

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L21/56 ,  H01L23/367

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US10705293B2

公开(公告)日：2020-07-07

申请号：US16061540

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Darmawikarta ,  Rahul Jain ,  Sri Ranga Sai Boyapati ,  Maroun Moussallem ,  Rahul N. Manepalli ,  Srinivas Pietambaram

IPC: G02B6/122 ,  G02B6/132 ,  H01P5/107 ,  G02B6/134 ,  G02B6/12

Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.

公开(公告)号：US20190393145A1

公开(公告)日：2019-12-26

申请号：US16554008

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US10431537B1

公开(公告)日：2019-10-01

申请号：US16014134

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20190157210A1

公开(公告)日：2019-05-23

申请号：US16097597

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L23/498 ,  H01L29/786 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/522 ,  H01L23/525 ,  H01L23/538 ,  H01L23/5384 ,  H01L27/1218 ,  H01L28/60 ,  H01L29/786 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.

公开(公告)号：US20190006457A1

公开(公告)日：2019-01-03

申请号：US15638044

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Kristof Darmawikarta ,  Robert Alan May ,  Sandeep Gaan

IPC: H01L49/02 ,  H01L23/522

Abstract: A semiconductor device may include a plurality of layers of a substrate. A die may be coupled to at least one of the plurality of layers of the substrate. A passive electrical component may be integrally formed within the layers of the substrate. The passive electrical component may be a resistor or a capacitor. One or more conductors may be configured to allow electrical communication between the passive electrical component and the die. The one or more conductors may be integrally formed within the plurality of layers of the substrate.

公开(公告)号：US09953959B1

公开(公告)日：2018-04-24

申请号：US15463523

申请日：2017-03-20

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Robert Alan May ,  Yikang Deng ,  Amruthavalli Pallavi Alur ,  Sheng Li ,  Chong Zhang ,  Sri Chaitra Jyotsna Chavali ,  Amanda E. Schuckman

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4817 ,  H01L21/486 ,  H01L25/50 ,  H01L2225/0652 ,  H01L2225/06548

Abstract: A metal protected fan-out cavity enables assembly of a package-on-package (PoP) integrated circuit while reducing PoP solder spacing and overall z-height. A horizontal fan-out conductor provides a contact between a die contact and a lower package via. A metal protection layer may be used during manufacture to protect the fan-out conductor, such as providing a laser stop during laser skiving. The metal protection layer materials and an etching solution may be selected to allow for subsequent removal via etching while leaving the fan-out conductor intact. The metal protection layer and fan-out conductor materials may also be selected to reduce or eliminate formation of an intermetallic compound (IMC) between the metal protection layer and the fan-out conductor.