公开(公告)号：US11594637B2

公开(公告)日：2023-02-28

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Stephen Snyder ,  Biswajeet Guha ,  William Hsu ,  Urusa Alaan ,  Tahir Ghani ,  Michael K. Harper ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US11581420B2

公开(公告)日：2023-02-14

申请号：US17227165

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Andrew W. Veoh ,  Tahir Ghani ,  Atul Madhavan ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

公开(公告)号：US20220415708A1

公开(公告)日：2022-12-29

申请号：US17358903

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Tahir Ghani ,  Patrick Keys ,  Aaron Lilak ,  Anand Murthy ,  Cory Weber

IPC: H01L21/768 ,  H01L29/10 ,  H01L27/088 ,  H01L25/07 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.

公开(公告)号：US20220406907A1

公开(公告)日：2022-12-22

申请号：US17821209

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert W. Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L23/29 ,  H01L29/78 ,  H01L29/45

Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US11527640B2

公开(公告)日：2022-12-13

申请号：US16238978

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Tahir Ghani ,  Stephen Cea ,  Biswajeet Guha

IPC: H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

公开(公告)号：US11521968B2

公开(公告)日：2022-12-06

申请号：US16024671

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Stephen Cea ,  Biswajeet Guha ,  Anupama Bowonder ,  Tahir Ghani

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US11495496B2

公开(公告)日：2022-11-08

申请号：US17141157

申请日：2021-01-04

Applicant: Intel Corporation

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/306 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/66 ,  H01L21/28 ,  H01L23/535 ,  H01L29/06 ,  H01L21/32

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US11476344B2

公开(公告)日：2022-10-18

申请号：US17643742

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L21/28 ,  H01L21/76 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/165 ,  H01L21/285 ,  H01L21/768

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US11444205B2

公开(公告)日：2022-09-13

申请号：US16143001

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Matthew Metz ,  Benjamin Chu-Kung ,  Abhishek Sharma ,  Van H. Le ,  Miriam R. Reshotko ,  Christopher J. Jezewski ,  Ryan Arch ,  Ande Kitamura ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Lawrence Wong ,  Tahir Ghani

IPC: H01L29/786 ,  H01L23/31 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L27/24 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US11417770B2

公开(公告)日：2022-08-16

申请号：US16142075

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Nazila Haratipour ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Shriram Shivaraman ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Arnab Sen Gupta

IPC: H01L29/786 ,  H01L29/49 ,  H01L27/108 ,  H01L29/66 ,  H01L27/24

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.