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    HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO
    43.
    发明申请
    HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO 有权

    公开(公告)号：US20170111059A1

    公开(公告)日：2017-04-20

    申请号：US15393599

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/40 ,  H03M7/30

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

    Heterogeneous compression architecture for optimized compression ratio
    45.
    发明授权
    Heterogeneous compression architecture for optimized compression ratio 有权
    用于优化压缩比的异构压缩架构

    公开(公告)号：US09537504B1

    公开(公告)日：2017-01-03

    申请号：US14866115

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes a storage device to store data and a processor, operably coupled to the storage device, the processor to receive a token stream comprising a plurality of tokens generated based on a byte stream comprising a plurality of bytes, wherein each token in the token stream comprises at least one symbol associated with a respective byte in the byte stream, and wherein the at least one symbol represents one of the respective byte, a length of a first byte string starting from the respective byte, or a byte distance between the first byte string and a matching second byte string, generate a graph comprising a plurality of nodes and edges based on the token stream, wherein each token in the token stream is associated with a respective node connected by at least one edge to another node, and wherein the at least one edge is associated with a cost function to encode the at least one symbol stored in the each token, identify, based on the graph, a path between a first node associated with a beginning token of the token stream and an end node associated with a last token of the token stream, wherein the path comprises a subset of nodes and edges linking the subset of nodes, and perform variable-length encoding of a subset of tokens associated with the subset of nodes to generate an output data.

    Abstract translation: 处理设备包括存储数据的存储设备和可操作地耦合到存储设备的处理器，处理器接收包括基于包括多个字节的字节流生成的多个令牌的令牌流，其中， 标记流包括与字节流中的相应字节相关联的至少一个符号，并且其中至少一个符号表示相应字节中的一个，从相应字节开始的第一字节串的长度，或 第一字节串和匹配的第二字节串，基于令牌流生成包括多个节点和边的图形，其中令牌流中的每个令牌与由至少一个边缘连接到另一个节点的相应节点相关联，以及 其中所述至少一个边缘与成本函数相关联，以对存储在每个令牌中的所述至少一个符号进行编码，基于所述图表来识别第一点之间的路径 e与令牌流的开始令牌和与令牌流的最后一个令牌相关联的结束节点相关联，其中该路径包括链接节点子集的节点和边缘的子集，并且执行子集的子集的可变长度编码 与节点子集相关联的令牌以生成输出数据。

    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES)
    50.
    发明申请
    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) 审中-公开
    实施高级加密标准（AES）的架构和指导

    公开(公告)号：US20160119122A1

    公开(公告)日：2016-04-28

    申请号：US14947944

    申请日：2015-11-20

    Applicant: INTEL CORPORATION

    Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    IPC: H04L9/06 ,  H04L9/14

    Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

    Abstract translation: 提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。 提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。 除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

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