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公开(公告)号：US20120170389A1
公开(公告)日：2012-07-05
申请号：US13416905
申请日：2012-03-09
IPC分类号： G11C8/18
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/405 , G11C7/222 , G11C8/18 , G11C11/4063 , G11C11/4072 , G11C11/4096
摘要： A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit comprises an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.
摘要翻译： 公开了一种用于基于闪光灯的存储器系统的存储器控制器。 存储器控制器包括用于产生相对于第一时钟信号具有预定定时关系的控制信号的电路，用于接收控制信号的电路，以及响应于限定读选通信号对读数据进行采样的接收器。 接收电路包括用于接收由半导体存储器件发送的外部读取选通信号的输入端，用于使控制信号与接收的读取选通信号同步以具有相对于彼此的公共定时关系的电路， 基于同步控制信号的选通信号。
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公开(公告)号：US20110156776A1
公开(公告)日：2011-06-30
申请号：US13042276
申请日：2011-03-07
申请人： Jade M. Kizer
发明人： Jade M. Kizer
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , G06F1/10 , H03L7/07 , H03L7/0814
摘要： A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.
摘要翻译： 具有时钟保持功能的锁定环路电路。 锁定环电路包括选择电路，相位混合电路，保持信号发生器和锁存电路。 选择电路响应于选择信号选择多个相位值中的一个，并且相位混合电路产生具有根据所选相位值的相位角的第一时钟信号。 保持信号发生器响应于选择信号的转变而置位保持信号，并且锁存电路响应于保持信号的断言而锁存第一时钟信号的状态。
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公开(公告)号：US20100254204A1
公开(公告)日：2010-10-07
申请号：US12721520
申请日：2010-03-10
申请人： Scott C. Best , Jade M. Kizer
发明人： Scott C. Best , Jade M. Kizer
CPC分类号： G06F13/4059
摘要： A method is disclosed comprising detecting an edge-transition of a strobe signal using hysteresis, the strobe signal originating in a first clock domain. A count is controlled in a first direction in response to the detected edge-transition. The count is controlled in a second direction in response to an edge-transition of a clock signal, the clock signal originating in a second clock domain. Data is interfaced between the first and second clock domains in response to the count.
摘要翻译： 公开了一种方法，包括使用滞后来检测选通信号的边沿转变，该选通信号源自第一时钟域。 响应于检测到的边缘转变，计数在第一方向上被控制。 响应于时钟信号的边沿转换，计数被控制在第二方向上，时钟信号源自第二时钟域。 响应于计数，数据在第一和第二时钟域之间接口。
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公开(公告)号：US20100188910A1
公开(公告)日：2010-07-29
申请号：US12596535
申请日：2008-04-18
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.
摘要翻译： 用于同步选通存储器系统10的系统和方法。在存储器读取和/或存储器写入操作期间，根据本地时钟信号71/73在数据目的地50/55处对相应的数据选通进行采样。 基于采样结果，数据选通和本地时钟信号同步。 以这种方式，数据与本地时钟信号同步，使得可以根据本地时钟信号而不是数据选通来执行数据目的地的数据采样。
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公开(公告)号：US08498344B2
公开(公告)日：2013-07-30
申请号：US12999495
申请日：2009-06-18
申请人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
发明人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.
摘要翻译： 数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。 设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。 可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。 检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。
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46.发明申请Clock and Data Recovery Employing Piece-Wise Estimation on the Derivative of the Frequency 有权时钟和数据恢复采用对频率微分的智慧估计公开(公告)号：US20130136220A1
公开(公告)日：2013-05-30
申请号：US13674812
申请日：2012-11-12
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.
摘要翻译： 一种用于执行时钟和数据恢复的系统和方法。 根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。
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公开(公告)号：US20130039396A1
公开(公告)日：2013-02-14
申请号：US13367197
申请日：2012-02-06
申请人： Jade M. Kizer
发明人： Jade M. Kizer
CPC分类号： H03L7/0805 , G06F1/10 , H03L7/07 , H03L7/0814
摘要： A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.
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公开(公告)号：US08243484B2
公开(公告)日：2012-08-14
申请号：US12532914
申请日：2008-03-27
申请人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
发明人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
IPC分类号： G11C5/02
CPC分类号： G06F13/4239 , G11C5/02 , G11C5/04 , H05K1/0237 , H05K1/181 , H05K2201/10159 , Y02P70/611
摘要： A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data signal lines and to a portion of the at least two strobe signal lines such that the devices do not share any of the N data signal lines and such that the devices do not share any of the strobe signal lines. The memory system further includes a controller 45 to communicate in parallel with the first and second memory devices through the N data signal lines and the at least two strobe signal lines.
摘要翻译： 存储器系统包括电路板40，其包括N条数据信号线60,65和至少两个选通信号线70,75以及固定到电路板的相对表面40a，40b的第一和第二存储器件50,55。 每个存储器件耦合到N个数据信号线的一部分和至少两个选通信号线的一部分，使得器件不共享N个数据信号线中的任何一个，并且使得器件不共享 选通信号线。 存储系统还包括控制器45，通过N个数据信号线和至少两个选通信号线与第一和第二存储器装置并行通信。
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公开(公告)号：US08068357B2
公开(公告)日：2011-11-29
申请号：US12204728
申请日：2008-09-04
申请人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
发明人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
IPC分类号： G11C5/06
摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.
摘要翻译： 存储器控制器以两种模式操作以支持不同类型的存储器件。 在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。 参考电压使用可替换地用于例如电极的焊盘传送。 定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。
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50.发明申请公开(公告)号：US20110051854A1
公开(公告)日：2011-03-03
申请号：US12920806
申请日：2009-02-19
申请人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
发明人： Jade M. Kizer , John Wilson , Lei Luo , Frederick Ware , Jared L. Zerbe
IPC分类号： H04L27/06
CPC分类号： H03M13/47 , H04L25/4919
摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols, and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
摘要翻译： 描述电路的实施例。 在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。 此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。 另外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡，以及M个符号集合中的第二值的多个实例，以及如果不平衡 被检测到，它确定了错误条件。
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