公开(公告)号：US10056404B2

公开(公告)日：2018-08-21

申请号：US14989955

申请日：2016-01-07

申请人： Jaeduk Lee ,  Youngwoo Park

发明人： Jaeduk Lee ,  Youngwoo Park

IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/06

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573

摘要： The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

公开(公告)号：US20170011996A1

公开(公告)日：2017-01-12

申请号：US15201922

申请日：2016-07-05

申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。

公开(公告)号：US09337207B2

公开(公告)日：2016-05-10

申请号：US14191542

申请日：2014-02-27

申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.

摘要翻译： 半导体存储器件包括：衬底，其包括单元区域和互连区域;相邻的从单元区域中的衬底垂直延伸的第一和第二排垂直沟道以及堆叠在衬底上的字线层。 每层包括第一行垂直通道通过的第一字线和第二行垂直通道通过的第二字线，并且字线包括延伸到互连区域中的相应字线焊盘。 隔离图案分离单元区域和互连区域中的第一和第二字线。 第一和第二多个接触插塞设置在互连区域中的隔离图案的相对侧上，并与字线焊盘接触。

公开(公告)号：US09281019B2

公开(公告)日：2016-03-08

申请号：US14057669

申请日：2013-10-18

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： G11C5/06 ,  G11C5/02 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。

公开(公告)号：US09224429B2

公开(公告)日：2015-12-29

申请号：US14635588

申请日：2015-03-02

申请人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： G11C5/02 ,  H01L27/115 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

公开(公告)号：US09019739B2

公开(公告)日：2015-04-28

申请号：US14152440

申请日：2014-01-10

申请人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： G11C5/02 ,  H01L27/115 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

摘要翻译： 根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧， 平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

公开(公告)号：US20140197469A1

公开(公告)日：2014-07-17

申请号：US14150452

申请日：2014-01-08

申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

IPC分类号： H01L27/105

CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

公开(公告)号：US20140160828A1

公开(公告)日：2014-06-12

申请号：US14057669

申请日：2013-10-18

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： G11C5/06

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。

公开(公告)号：US08379456B2

公开(公告)日：2013-02-19

申请号：US12901605

申请日：2010-10-11

申请人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Youngwoo Park ,  Jongsun Sel ,  Jintaek Park

发明人： Chan Park ,  Changseok Kang ,  Sung-Il Chang ,  Youngwoo Park ,  Jongsun Sel ,  Jintaek Park

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/10

摘要： Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation.

摘要翻译： 提供了非易失性存储器件及其操作方法。 非易失性存储器件包括：连接到虚拟位线的虚拟单元; 以及在编程操作期间向虚拟位线提供虚拟位线电压的虚拟位线偏置电路，其中，由于虚拟位线电压，至少一个虚设单元被编程为具有低于顶部的阈值电压 在程序运行期间高于擦除状态。

公开(公告)号：US20120068247A1

公开(公告)日：2012-03-22

申请号：US13217416

申请日：2011-08-25

申请人： CHANGHYUN LEE ,  Byoungkeun Son ,  Youngwoo Park

发明人： CHANGHYUN LEE ,  Byoungkeun Son ,  Youngwoo Park

IPC分类号： H01L27/088

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.

摘要翻译： 提供三维半导体器件。 这些装置可以包括配置成从基板向上延伸的间隙填充绝缘图案和由间隙填充绝缘图案的侧壁限定的电极结构。 可以在相邻的间隙填充绝缘图案之间提供垂直结构以穿透电极结构，并且垂直结构可以包括垂直结构的第一行和第二行。 可以在第一和第二排垂直结构之间提供分离图案，并且包括分离半导体层。 分离图案沿着平行于第一和第二排垂直结构的方向延伸。