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    Methods of forming hemisperical grained silicon on a template on a semiconductor work object
    42.
    发明申请
    Methods of forming hemisperical grained silicon on a template on a semiconductor work object 审中-公开
    在半导体工件上的模板上形成半晶粒硅的方法

    公开(公告)号：US20050051082A1

    公开(公告)日：2005-03-10

    申请号：US10943612

    申请日：2004-09-17

    Applicant: Guoqing Chen ,  James Pan

    Inventor： Guoqing Chen ,  James Pan

    IPC: H01L21/02 ,  C30B23/00 ,  C30B1/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

    CPC classification number: H01L28/84 ,  H01L28/90

    Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

    Abstract translation: 本发明提供一种制备用于形成HSG结构的硅晶片的表面的方法。 该方法考虑提供具有包含在BPSG中形成的多晶硅的至少一个HSG模板的晶片，HSG模板被二氧化硅覆盖。 用清洁剂处理晶片以清洁晶片的表面。 接下来，用调理剂处理晶片。 调理剂从HSG模板中除去天然氧化物，而不会过度蚀刻结构BPSG。 优选地，调理剂还在HSG模板上除去薄层的多晶硅。 然后将晶片转移到用于HSG形成的处理室。

    Methods of forming hemispherical grained silicon on a template on a semiconductor work object
    43.
    发明授权
    Methods of forming hemispherical grained silicon on a template on a semiconductor work object 失效
    在半导体工件上的模板上形成半球形晶粒硅的方法

    公开(公告)号：US06835617B2

    公开(公告)日：2004-12-28

    申请号：US10361107

    申请日：2003-02-07

    Applicant: Guoqing Chen ,  James Pan

    Inventor： Guoqing Chen ,  James Pan

    IPC: H01L218242

    CPC classification number: H01L28/84 ,  H01L28/90

    Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

    Abstract translation: 本发明提供一种制备用于形成HSG结构的硅晶片的表面的方法。 该方法考虑提供具有包含在BPSG中形成的多晶硅的至少一个HSG模板的晶片，HSG模板被二氧化硅覆盖。 用清洁剂处理晶片以清洁晶片的表面。 接下来，用调理剂处理晶片。 调理剂从HSG模板中除去天然氧化物，而不会过度蚀刻结构BPSG。 优选地，调理剂还在HSG模板上除去薄层的多晶硅。 然后将晶片转移到用于HSG形成的处理室。

    High selectivity etching process for oxides
    44.
    发明授权
    High selectivity etching process for oxides 失效
    氧化物的高选择性蚀刻工艺

    公开(公告)号：US06355182B2

    公开(公告)日：2002-03-12

    申请号：US09780166

    申请日：2001-02-09

    Applicant: Randhir Thakur ,  James Pan

    Inventor： Randhir Thakur ,  James Pan

    IPC: D44C122

    CPC classification number: H01L28/40 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116

    Abstract: A process for etching oxides having differing densities which is not only highly selective, but which also produces uniform etches is provided and includes the steps of providing an oxide layer on a surface of a substrate, exposing the oxide layer to a liquid comprising a halide-containing species, and exposing the oxide layer to a gas phase comprising a halide-containing species. The process desirably is used to selectively etch a substrate surface in which the surface of the substrate includes on a first portion thereof a first silicon oxide and on a second portion thereof a second silicon oxide, with the first silicon oxide being relatively more dense than the second silicon oxide, such as, for example, a process which forms a capacitor storage cell on a semiconductor substrate.

    Abstract translation: 提供了不仅具有高选择性但也产生均匀蚀刻的具有不同密度的氧化物的方法，包括以下步骤：在衬底的表面上提供氧化物层，将氧化物层暴露于包含卤化物 - 并将氧化物层暴露于含有卤化物的物质的气相中。 该方法理想地用于选择性地蚀刻其中衬底的表面在其第一部分上包含第一氧化硅的衬底表面，并且在其第二部分上选择性地蚀刻第二氧化硅，其中第一氧化硅相对于 第二氧化硅，例如在半导体衬底上形成电容器存储单元的工艺。

    Structure related to a thick bottom dielectric (TBD) for trench-gate devices
    46.
    发明授权
    Structure related to a thick bottom dielectric (TBD) for trench-gate devices 有权
    与沟槽栅极器件的厚底部电介质（TBD）有关的结构

    公开(公告)号：US08669623B2

    公开(公告)日：2014-03-11

    申请号：US12870600

    申请日：2010-08-27

    Applicant: James Pan ,  Christopher Lawrence Rexer

    Inventor： James Pan ,  Christopher Lawrence Rexer

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/8725

    Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

    Abstract translation: 包括屏蔽栅极的半导体结构如下形成。 使用掩模在半导体区域中形成多个沟槽。 掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。 形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。 沿每个沟槽的底部形成厚底部电介质（TBD）。 第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。 屏蔽电极形成在每个沟槽的底部。 在每个沟槽中的屏蔽电极之上形成栅电极。

    Structure and method for semiconductor power devices
    47.
    发明授权
    Structure and method for semiconductor power devices 有权
    半导体功率器件的结构和方法

    公开(公告)号：US08541840B2

    公开(公告)日：2013-09-24

    申请号：US13028054

    申请日：2011-02-15

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L27/12

    CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/78624

    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.

    Abstract translation: 半导体器件包括在衬底上的绝缘体上半导体区域。 绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。 该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。 该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。 双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。 因此，MOS晶体管的漏极也用作双极晶体管的发射极。 此外，栅极和基极通过电阻元件耦合。

    "> Novel Very Fast Optic Nonvolatile Memory with Alternative Carrier Lifetimes and Bandgap Energies, Optic Random Access, and Mirrored
    49.
    发明申请
    Novel Very Fast Optic Nonvolatile Memory with Alternative Carrier Lifetimes and Bandgap Energies, Optic Random Access, and Mirrored "Fly-back" Configurations 审中-公开
    具有替代载波寿命和带隙能量的新型非常快速的非易失性存储器，光学随机存取和镜像“反馈”配置

    公开(公告)号：US20120292676A1

    公开(公告)日：2012-11-22

    申请号：US13113048

    申请日：2011-05-21

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L31/113

    CPC classification number: G11C13/047

    Abstract: The present invention is for a fast optic nonvolatile memory cell (FONM) that operates with a speed >1000000 times faster than the commercially available FLASH memory. The information (or charges) can be entered into the FONM cell by switching on a built-in laser or LED (Light Emitting Diode). Excited by the lights, and driven by electric fields, the regions of low carrier lifetimes thermally generate excess electrons or positive charges to fill the storage gaps or interfaces. To detect the stored information, two BJTs (Bipolar Junction Transistors) are arranged in a mirrored configuration—with alternative regions of high or low carrier lifetimes and bandgap energies. By comparing the BJT “fly-back” characteristics a voltage difference can be detected as a signal of whether the information is stored or not stored.

    Abstract translation: 本发明用于快速光学非易失性存储单元（FONM），其以比市售的闪速存储器快1000000倍的速度运行。 通过打开内置激光或LED（发光二极管）可以将信息（或电荷）输入到FONM单元。 由光激发，由电场驱动，低载流子寿命的区域会产生过量的电子或正电荷，以填充储存间隙或界面。 为了检测存储的信息，两个BJT（双极结晶体管）被布置成镜像配置 - 具有高或低载波寿命和带隙能量的替代区域。 通过比较BJT回扫特性，可以检测电压差是否存储信息或不存储信息。

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