公开(公告)号：US5778407A

公开(公告)日：1998-07-07

申请号：US667241

申请日：1996-06-21

申请人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael Alan Fetterman ,  Robert P. Colwell ,  Frederick Jay Pollack

发明人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael Alan Fetterman ,  Robert P. Colwell ,  Frederick Jay Pollack

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/06

CPC分类号： G06F12/0888 ,  G06F12/1027 ,  G06F2212/206

摘要： A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

摘要翻译： 包括多个范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在前面的执行阶段可用就允许确定存储器操作特性 缓存访问。 此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器条目，并且存储器类型确定电路被布置在页面未命中处理器中，从而允许确定存储器类型 同时确定物理地址。

公开(公告)号：US5778245A

公开(公告)日：1998-07-07

申请号：US204861

申请日：1994-03-01

申请人： David B. Papworth ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert P. Colwell ,  Michael A. Fetterman ,  Shantanu R. Gupta ,  James S. Griffith

发明人： David B. Papworth ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert P. Colwell ,  Michael A. Fetterman ,  Shantanu R. Gupta ,  James S. Griffith

IPC分类号： G06F9/38 ,  G06F9/50 ,  G06F15/82

CPC分类号： G06F9/5016 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.

摘要翻译： 一种用于以有效方式动态地将微处理器资源的条目分配给特定指令以有效利用缓冲器大小和资源的方法和装置。 流水线和超标量微处理器能够推测性地执行指令并进行无序处理。 微处理器内的资源包括存储缓冲器，加载缓冲器，重新排序缓冲器和保留站。 重排序缓冲器包含较大的一组物理寄存器，并且还包含与推测指令相关的信息，并且保留站包括与待执行的指令相关的信息。 加载缓冲区仅分配给加载指令，对从分配管理到指令退出的指令有效。 存储缓冲区仅被分配用于存储指令，并且对于分配的指令有效以存储性能。 保留站被分配给大多数指令，并且对于从分配到指令分派的指令是有效的。 重新排序缓冲区被分配给所有指令，并且对于从分配到退休的给定指令是有效的。 在保留站不存在的情况下顺序地分配负载缓冲器，存储缓冲器和重排序缓冲器。 动态执行资源分配（根据操作需要），而不是作为每个操作附加的一整套资源。 使用上述分配方案，可以实现微处理器资源的高效利用。

公开(公告)号：US5584038A

公开(公告)日：1996-12-10

申请号：US633905

申请日：1996-04-17

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度的推测执行的微处理器的应用程序。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5561814A

公开(公告)日：1996-10-01

申请号：US171528

申请日：1993-12-22

申请人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman ,  Robert P. Colwell ,  Frederick J. Pollack

发明人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman ,  Robert P. Colwell ,  Frederick J. Pollack

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/10

CPC分类号： G06F12/0888 ,  G06F12/1027 ,  G06F2212/206

摘要： A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

摘要翻译： 包括多个地址范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在执行阶段中可用，就允许确定存储器类型 缓存访问。 此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器入口。 存储器类型确定电路设置在页面未命中处理器中，从而允许在确定物理地址的同时确定存储器类型。

公开(公告)号：US5636374A

公开(公告)日：1997-06-03

申请号：US470842

申请日：1995-06-06

申请人： Scott D. Rodgers ,  Keshavan K. Tiruvallur ,  Michael W. Rhodehamel ,  Kris G. Konigsfeld ,  Andrew F. Glew ,  Haitham Akkary ,  Milind A. Karnik ,  James A. Brayton

发明人： Scott D. Rodgers ,  Keshavan K. Tiruvallur ,  Michael W. Rhodehamel ,  Kris G. Konigsfeld ,  Andrew F. Glew ,  Haitham Akkary ,  Milind A. Karnik ,  James A. Brayton

IPC分类号： G06F9/312 ,  G06F12/08 ,  G06F12/10 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F12/0891 ,  G06F12/1027

摘要： In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.

摘要翻译： 在微处理器中，用于执行存储器功能并发布总线周期的装置和方法。 特殊的微指令存储在微码ROM中。 这些微指令用于执行存储器功能并产生特殊的总线周期。 最初，对于这些特殊微指令之一产生与要执行的请求操作相对应的地址。 该特殊微指令及其地址然后通过总线传输到微处理器的各个单元。 当每个单元接收微指令时，它根据该地址确定该微指令是否被忽略。 如果特定单元忽略微指令，则微指令将转发到管道中的后续单元进行处理。 否则，如果该特定单元执行由微指令的地址指定的请求操作。

公开(公告)号：US5584001A

公开(公告)日：1996-12-10

申请号：US509331

申请日：1995-07-31

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  Andrew F. Glew ,  Subramanian Natarajan

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  Andrew F. Glew ,  Subramanian Natarajan

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3806 ,  G06F9/3844

摘要： A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.

摘要翻译： 分支预测机制，保持分支目标缓冲区中每个分支指令的推测历史和实际历史。 实际的分支历史包含分支指令的完全解决事件的分支历史。 投机分支历史包含实际历史加上分支机构最近分支预测的“历史”。 如果推测分支历史记录包含任何最近的预测，则设置推测位。 当猜测位置位时，表示有一个分支的推测历史。 因此，当设置推测位时，推测历史用于进行分支预测。 如果对分行进行错误预测，则推测位将被清除，因为投机历史记录包含不准确的分支历史记录。

公开(公告)号：US5854914A

公开(公告)日：1998-12-29

申请号：US711096

申请日：1996-09-10

申请人： Milind Bodas ,  Glenn J. Hinton ,  Andrew F. Glew

发明人： Milind Bodas ,  Glenn J. Hinton ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3816 ,  G06F9/3834 ,  G06F9/3842

摘要： A method and apparatus for executing a misaligned load. The method begins with receiving a load request to load data from a first memory location. An entry in a store buffer is tested to determine whether the entry corresponds to the first memory location. The entry is also tested to determine whether the entry corresponds to a second memory location subsequent to the first memory location. The load request is blocked if the entry corresponds to the first memory location or the second memory location. After a store operation for the store buffer entry is executed, the load request may be unblocked. The apparatus is a processor or a computer system comprising a load buffer capable of storing a load request address in response to a load request. The processor includes an incrementing circuit that generates an incremented load request address. The processor also includes a store buffer containing a portion of a store request address. The store buffer includes comparison circuitry that compares the portion of the store request address to the load request and the incremented load request address, and generates a blocking signal if the either of the load request address and the incremented load request correspond to the store request address.

摘要翻译： 一种用于执行不对中负载的方法和装置。 该方法从接收到从第一存储器位置加载数据的加载请求开始。 测试存储缓冲区中的条目以确定条目是否对应于第一存储器位置。 还测试该条目以确定条目是否对应于第一存储器位置之后的第二存储器位置。 如果条目对应于第一个存储器位置或第二个存储器位置，则加载请求被阻止。 在执行存储缓冲器条目的存储操作之后，加载请求可以被解除阻塞。 该装置是包括能够响应于负载请求而存储加载请求地址的加载缓冲器的处理器或计算机系统。 处理器包括生成递增的加载请求地址的递增电路。 该处理器还包括一个包含存储请求地址的一部分的存储缓冲器。 存储缓冲器包括比较电路，其将存储请求地址的部分与加载请求和增加的加载请求地址进行比较，并且如果加载请求地址和增加的加载请求中的任一个对应于存储请求地址，则产生阻塞信号 。

公开(公告)号：US06047369A

公开(公告)日：2000-04-04

申请号：US204521

申请日：1994-02-28

申请人： Robert P. Colwell ,  Andrew F. Glew ,  Atiq A. Bajwa ,  Glenn J. Hinton ,  Michael A. Fetterman

发明人： Robert P. Colwell ,  Andrew F. Glew ,  Atiq A. Bajwa ,  Glenn J. Hinton ,  Michael A. Fetterman

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions. Also, static and dynamic flag masks are associated with particular instructions and indicate which flags are capable of being updated by a particular instruction and also indicate which flags are actually updated by the instruction. Static flag masks are used in flag renaming and dynamic flag masks are used at retirement. The invention also discovers cases in which a flag register is required that is a superset of the previously renamed flag register portion.

摘要翻译： 一种用于重命名寄存器别名表（“RAT”）中的标志以增加处理器并行性并且还提供和使用与各个指令相关联的标志掩码的机制和方法。 为了减少并发处理的指令之间的数据依赖性，这些指令使用的标志被重命名。 通常，RAT单元提供寄存器重命名以提供比通常在给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）内通常可用的更大的物理寄存器集，以消除指令之间的虚假数据依赖性 这降低了微处理器的整体超标量处理性能。 重命名的标志寄存器包含几个标志位，各种标志位可能被不同的指令更新或读取。 此外，静态和动态标志掩码与特定指令相关联，并且指示哪些标志能够被特定指令更新，并且还指示哪些标志实际上被指令更新。 在标志重命名中使用静态标志掩码，退休时使用动态标志掩码。 本发明还发现需要作为先前重命名的标志寄存器部分的超集的标志寄存器的情况。

公开(公告)号：US5613083A

公开(公告)日：1997-03-18

申请号：US316089

申请日：1994-09-30

申请人： Andrew F. Glew ,  Haitham Akkary ,  Glenn J. Hinton

发明人： Andrew F. Glew ,  Haitham Akkary ,  Glenn J. Hinton

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/684

摘要： A translation lookaside buffer is described for use with a microprocessor capable of speculative and out-of-order processing of memory instructions. The translation lookaside buffer is non-blocking in response to translation lookaside buffer misses requiring page table walks. Once a translation lookaside buffer miss is detected, a page table walk is initiated to satisfy the miss. During the page table walk, additional memory instructions are processed by the translation lookaside buffer. Any additional instructions which cause translation lookaside buffer hits are merely processed by the translation lookaside buffer. However, instructions causing translation lookaside buffer misses while the page table walk is being performed are blocked pending completion of the page table walk. Once the page table walk is completed the blocked instructions are reawakened and are again processed by the translation lookaside buffer. Global and selective wakeup mechanisms are described. An implementation wherein the non-blocking translation lookaside buffer is provided within a microprocessor capable of speculative and out-of-order processing is also described.

摘要翻译： 描述了翻译后备缓冲器用于能够对存储器指令进行推测和无序处理的微处理器。 翻译后备缓冲区是响应于需要页表行进的翻译后备缓冲区错误而不阻塞的。 一旦检测到翻译后备缓存器未命中，则启动页表步行以满足缺失。 在页表行走期间，另外的存储器指令由翻译后备缓冲器处理。 导致翻译后备缓冲区命中的任何附加指令仅由翻译后备缓冲器处理。 然而，正在执行页表行进时导致翻译后备缓冲区未命中的指令在页表行进完成之前被阻止。 一旦页表行进完成，阻塞的指令被重新唤醒，并由翻译后备缓冲区再次处理。 描述了全局和选择性唤醒机制。 还描述了其中在能够进行推测和无序处理的微处理器内提供非阻塞转换后备缓冲器的实现。

公开(公告)号：US5751996A

公开(公告)日：1998-05-12

申请号：US767799

申请日：1996-12-17

申请人： Andrew F. Glew ,  Glenn J. Hinton

发明人： Andrew F. Glew ,  Glenn J. Hinton

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/30043 ,  G06F12/0804 ,  G06F12/0888 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857

摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed in accordance with any one of a number of processing protocols including write-through processing, write-back processing, write-protect processing, restricted-cacheability processing, uncacheable speculatable write-combining processing, or uncacheable processing. By providing memory-type information explicitly within the microprocessor, the type of memory identified by a micro-instruction is known before the micro-instruction is processed. Accordingly, the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. For example, if the memory location identified by the micro-instruction is known to be uncacheable, a data cache unit is bypassed and external memory is accessed directly. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor capable of generating speculative memory micro-instruction. Also, the microprocessor may be only one of a number of microprocessors within a multiprocessor system.

摘要翻译： 识别包含有存储器位置范围的存储器类型的存储器类型值被明确地存储在微处理器内。 在处理诸如加载或存储之类的存储器微指令之前，为由存储器微指令识别的存储器位置确定存储器类型。 一旦已知存储器类型，存储器微指令根据多种处理协议中的任何一种被处理，包括直写处理，回写处理，写保护处理，限制高速缓存处理，不可缓存的可写入写入 - 组合处理或不可缓解的处理。 通过在微处理器内显式提供存储器类型信息，在微指令被处理之前，已经知道由微指令识别的存储器类型。 因此，处理微指令的协议可以有效地针对存储器类型进行定制。 例如，如果由微指令识别的存储器位置已知是不可缓存的，则旁路数据高速缓存单元，并直接访问外部存储器。 在示例性实施例中，微处理器是能够产生推测存储器微指令的无序微处理器。 此外，微处理器可能只是多处理器系统内的多个微处理器之一。