公开(公告)号：US07214583B2

公开(公告)日：2007-05-08

申请号：US11130983

申请日：2005-05-16

申请人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L21/8242

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US07205238B2

公开(公告)日：2007-04-17

申请号：US10971665

申请日：2004-10-21

申请人： Wei Pan ,  David R. Evans ,  Allen Burmaster

发明人： Wei Pan ,  David R. Evans ,  Allen Burmaster

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3212 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

摘要： A method of fabricating a CMR layer in a CMOS device using CMP to pattern the CMR layer includes preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate; depositing a layer of SiNx on the substrate; patterning and etching the SiNx layer to form a damascene trench over the bottom electrode; depositing a layer CMR material over the SiNx and in the damascene trench; removing the CMR material overlying the SiNx layer by CMP, leaving the CMR material in the damascene trench; and completing the CMOS structure.

摘要翻译： 使用CMP对CMR层进行图案化的CMOS器件中的CMR层的制造方法包括制备硅衬底，包括在硅衬底中制造底部电极; 在衬底上沉积一层SiN x x; 图案化和蚀刻SiN x层以在底部电极上形成镶嵌沟槽; 在SiN x x上和在镶嵌沟槽中沉积层CMR材料; 通过CMP去除覆盖SiN x层的CMR材料，将CMR材料留在镶嵌槽中; 并完成CMOS结构。

公开(公告)号：US07029924B2

公开(公告)日：2006-04-18

申请号：US10755654

申请日：2004-01-12

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

IPC分类号： H01L21/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。

公开(公告)号：US06927120B2

公开(公告)日：2005-08-09

申请号：US10442749

申请日：2003-05-21

申请人： Sheng Teng Hsu ,  Tingkal Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Teng Hsu ,  Tingkal Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L27/10 ,  G11C11/15 ,  G11C13/00 ,  H01L45/00 ,  H01L21/8242

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US06794198B1

公开(公告)日：2004-09-21

申请号：US10606057

申请日：2003-06-25

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans ,  Bruce D. Ulrich

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans ,  Bruce D. Ulrich

IPC分类号： H01L2100

CPC分类号： H01L21/31691 ,  C23C16/0209 ,  C23C16/40 ,  C23C16/56 ,  H01L21/31604

摘要： A method of forming a PGO thin film on a high-k dielectric includes preparing a silicon substrate, including forming a high-k gate oxide layer thereon; patterning the high-k gate oxide; annealing the substrate in a first annealing step; placing the substrate in a MOCVD chamber; depositing a PGO thin film by injecting a PGO precursor into the MOCVD chamber; and annealing the structure having a PGO thin film on a high-k gate oxide in a second annealing step.

摘要翻译： 在高k电介质上形成PGO薄膜的方法包括制备硅衬底，包括在其上形成高k栅极氧化物层; 图案化高k栅极氧化物; 在第一退火步骤中退火衬底; 将基板放置在MOCVD室中; 通过将PGO前体注入到MOCVD室中来沉积PGO薄膜; 以及在第二退火步骤中在高k栅极氧化物上退火具有PGO薄膜的结构。

公开(公告)号：US06586344B2

公开(公告)日：2003-07-01

申请号：US10261448

申请日：2002-09-30

申请人： Wei-Wei Zhuang ,  David R. Evans

发明人： Wei-Wei Zhuang ,  David R. Evans

IPC分类号： G01B533

CPC分类号： H01L21/31625 ,  C01G25/02 ,  C01G27/02 ,  C07F7/003 ,  C23C16/405 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/3141

摘要： A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.

公开(公告)号：US06579793B2

公开(公告)日：2003-06-17

申请号：US09820224

申请日：2001-03-27

申请人： Wei-Wei Zhuang ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： C23C1618

CPC分类号： C23C16/18 ,  C23C16/56 ,  H01L21/28556

摘要： A fabrication process provides for achieving high adhesion of CVD copper thin films on metal nitride substrates, and in particular, on substrates having an outermost TaN layer. The method comprises introducing a certain amount of water vapor to the initial copper thin film deposition stage and reducing the amount of fluorine in the interface of the copper and metal nitride substrate. These two process steps result in a copper thin film having improved adhesion to metal nitride substrates, including TaN substrates.

摘要翻译： 制造工艺提供了在金属氮化物衬底上，特别是在具有最外层TaN层的衬底上实现CVD铜薄膜的高附着性。 该方法包括将一定量的水蒸汽引入初始铜薄膜沉积阶段并减少铜和金属氮化物衬底的界面中的氟的量。 这两个工艺步骤导致具有改善的与金属氮化物衬底（包括TaN衬底）的粘附性的铜薄膜。

公开(公告)号：US06576293B2

公开(公告)日：2003-06-10

申请号：US09817836

申请日：2001-03-26

申请人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  David R. Evans

发明人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： C23C1618

CPC分类号： H01L21/28556

摘要： A method of forming a copper thin film by chemical vapor deposition, includes introducing a wafer into a chemical vapor deposition chamber; humidifying helium gas with water to form a wet helium gas for use as the atmosphere in the chemical vapor deposition chamber; depositing a copper seed layer at a wet helium flow rate of between about 5.0 sccm and 20.0 sccm during a wafer temperature rise from ambient temperature to between about 150° C. to 230° C.; and depositing a copper thin film layer at a wet helium flow rate of between about 0.2 sccm to 1.0 sccm and at a temperature of between about 150° C. to 230° C.

公开(公告)号：US06509268B1

公开(公告)日：2003-01-21

申请号：US09940739

申请日：2001-08-27

申请人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L2144

CPC分类号： H01L21/28556 ,  H01L21/76877

摘要： A method of forming a copper thin film on an integrated circuit substrate having a nitride component includes preparing the substrate; treating the substrate prior to copper deposition; depositing copper during a very short duration copper deposition step lasting between about ten seconds to 40 seconds; baking the substrate and the deposited copper for between about one minute to ten minutes at a temperature greater than 385° C.; and depositing copper during a long duration copper deposition step to deposit copper to the required thickness.

摘要翻译： 在具有氮化物成分的集成电路基板上形成铜薄膜的方法包括：准备所述基板; 在铜沉积之前处理衬底; 在持续约十秒至40秒的非常短的铜沉积步骤期间沉积铜; 在大于385℃的温度下烘烤基材和沉积的铜约1分钟至10分钟; 以及在长时间铜沉积步骤中沉积铜以将铜沉积到所需厚度。

公开(公告)号：US06274421B1

公开(公告)日：2001-08-14

申请号：US09004991

申请日：1998-01-09

申请人： Sheng Teng Hsu ,  David R. Evans ,  Tue Nguyen

发明人： Sheng Teng Hsu ,  David R. Evans ,  Tue Nguyen

IPC分类号： H01L218238

CPC分类号： H01L29/6659 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/82385 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

摘要： A MOS transistor is formed on a single crystal silicon substrate doped to form a conductive layer of a first type, and includes: an active region formed on said substrate; a source region and a drain region located in said active region, doped to form conductive channels of a second type; a metal gate region located in said active region between said source region and said drain region, wherein said metal gate has a width of less than one micron; a gate oxide region located over said gate region; an oxide region located over the structure; and a source electrode, a gate electrode and a drain electrode, each connected to their respective regions, and each formed of a combination of a contact metal and an electrode metal. An alternate embodiment includes a pair of MOS transistors which have an interconnect between their gate electrodes and the drain electrode of one transistor and the drain electrode of the other transistor.

摘要翻译： MOS晶体管形成在掺杂以形成第一类型的导电层的单晶硅衬底上，并且包括：形成在所述衬底上的有源区; 位于所述有源区中的源极区和漏极区，被掺杂以形成第二类型的导电沟道; 位于所述源极区域和所述漏极区域之间的所述有源区域中的金属栅极区域，其中所述金属栅极具有小于1微米的宽度; 位于所述栅极区域上方的栅极氧化物区域; 位于结构上方的氧化物区域; 以及源电极，栅电极和漏电极，各自连接到它们各自的区域，并且各自由接触金属和电极金属的组合形成。 替代实施例包括一对MOS晶体管，它们在其栅电极和一个晶体管的漏电极和另一晶体管的漏电极之间具有互连。