公开(公告)号：US6133746A

公开(公告)日：2000-10-17

申请号：US163414

申请日：1998-09-30

申请人： Peng Fang ,  Hao Fang

发明人： Peng Fang ,  Hao Fang

IPC分类号： G01N27/92 ,  H01L23/544 ,  G01R31/12 ,  H01L21/66

CPC分类号： H01L22/34 ,  G01N27/92

摘要： A method for determining a reliable gate oxide thickness for a transistor involves subjecting test transistors to an alternating current (AC) voltage until the test transistors break down. The breakdown times of the test transistors are measured and correlated with the corresponding gate oxide thickness of the test transistor to form a reliability model of the transistor. The reliable gate oxide thickness is determined by extrapolating the reliability model out to a predetermined period of time for which reliability is desired, for example, ten years.

摘要翻译： 用于确定晶体管的可靠栅极氧化物厚度的方法包括使测试晶体管经受交流（AC）电压，直到测试晶体管分解为止。 测量测试晶体管的击穿时间并与测试晶体管的相应栅极氧化物厚度相关联，以形成晶体管的可靠性模型。 可靠的栅极氧化物厚度通过将可靠性模型推断到需要可靠性的预定时间段（例如十年）来确定。

公开(公告)号：US6023085A

公开(公告)日：2000-02-08

申请号：US993910

申请日：1997-12-18

申请人： Hao Fang

发明人： Hao Fang

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

摘要： A method of forming a NAND-type flash memory device (200) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.

摘要翻译： 一种形成NAND型闪速存储器件（200）的方法包括：在芯区（305）中形成用于一个或多个闪存单元的层叠栅极闪速存储器结构（346），并形成具有第一栅极氧化物 336）和用于芯区（305）中的选择栅极晶体管（344）和外围区域（328）中的低电压晶体管（342）的栅极导体（338）。 另外，NAND型闪速存储器件（200）包括一个包含层叠栅极快闪存储器单元结构（346）和选择栅极晶体管（344）的核心区域（305）和包括一个 低压晶体管（342）和高压晶体管（350），其中选择栅晶体管（344）和低压晶体管（342）的结构基本相同。

公开(公告)号：US5661059A

公开(公告)日：1997-08-26

申请号：US423109

申请日：1995-04-18

申请人： David Liu ,  Hao Fang

发明人： David Liu ,  Hao Fang

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/6659 ,  H01L21/2256 ,  H01L21/28061 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/4933

摘要： A method for forming a set of p-channel devices with enhanced n-doping and penetration of boron into the channel region between the source and drain regions, thereby creating channel length independent p-channel threshold voltage behavior. Long channel and short channel transistors have approximately equal threshold voltages as (a) short channel effect is reduced with increased n-doping in short channel transistors (where boron penetration has little effect), and (b) the effects of boron penetration and increased n-doping are offset in longer channel transistors.

摘要翻译： 一种用于形成具有增强的n掺杂和硼渗透到源极和漏极区域之间的沟道区域中的p沟道器件的集合的方法，从而产生与沟道长度无关的p沟道阈值电压特性。 长通道和短沟道晶体管具有近似相等的阈值电压，如（a）短沟道效应随着短沟道晶体管（其中硼渗透几乎没有影响）的n掺杂增加而减小，（b）硼渗透和增加的n 掺杂在较长的沟道晶体管中偏移。

公开(公告)号：US5617357A

公开(公告)日：1997-04-01

申请号：US420989

申请日：1995-04-07

申请人： Sameer S. Haddad ,  Hao Fang

发明人： Sameer S. Haddad ,  Hao Fang

IPC分类号： G11C16/14 ,  H01L29/788 ,  G11C11/40

CPC分类号： H01L29/7885 ,  G11C16/14 ,  Y10S438/972

摘要： A floating gate cell memory device, such as an EPROM or flash EEPROM, with improved discharge speed. A negative bias is applied to the effective substrate during discharge. The negative bias increases the electric field near the junction, thereby increasing the number of hot holes which can be injected to the floating gate, improving discharge speed.

摘要翻译： 具有改善的放电速度的浮动栅极单元存储器件，例如EPROM或快闪EEPROM。 在放电期间，对有效衬底施加负偏压。 负偏压增加了接点附近的电场，从而增加了可以注入到浮动栅极的热孔数量，从而提高了放电速度。

公开(公告)号：US20120217563A1

公开(公告)日：2012-08-30

申请号：US13465649

申请日：2012-05-07

申请人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin

发明人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻通过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US08183619B1

公开(公告)日：2012-05-22

申请号：US09539458

申请日：2000-03-30

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

公开(公告)号：US07436703B2

公开(公告)日：2008-10-14

申请号：US11319908

申请日：2005-12-27

申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US07362615B2

公开(公告)日：2008-04-22

申请号：US11319260

申请日：2005-12-27

申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US07116174B2

公开(公告)日：2006-10-03

申请号：US10953897

申请日：2004-09-29

申请人： Hao Fang ,  Cameron Carroll Rabe

发明人： Hao Fang ,  Cameron Carroll Rabe

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： H03F1/302 ,  H03F2200/453

摘要： A method and apparatus for compensating a base current of a bipolar junction transistor by replicating operating conditions of the BJT in a compensating circuit. An output current of the compensating circuit is fractionally related to the base current and thus can be supplied to an operational circuit comprising the BJT to compensate the base current. In a preferred embodiment, the BJT is operated between BVCEO and BVCBO and the base current to be compensated flows from the BJT.

摘要翻译： 一种用于通过在补偿电路中复制BJT的工作条件来补偿双极结型晶体管的基极电流的方法和装置。 补偿电路的输出电流与基极电流分数有关，因此可以提供给包括BJT的运算电路以补偿基极电流。 在优选实施例中，BJT在BVCEO和BVCBO之间运行，待补偿的基极电流从BJT流出。

公开(公告)号：US20060134881A1

公开(公告)日：2006-06-22

申请号：US11013415

申请日：2004-12-17

申请人： Been-Jon Woo ,  Hao Fang ,  Mon-Chin Tsai

发明人： Been-Jon Woo ,  Hao Fang ,  Mon-Chin Tsai

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method of forming a trench isolation device capable of reducing corner recess comprising forming a pad oxide layer and a silicon nitride mask layer on a semiconductor base, and forming a trench by etching. Next, a liner oxide layer is formed on the semiconductor base and on the surface of the shallow trench. Then, the silicon nitride mask layer will be etched to reveal the corner. Finally, a layer of oxide is formed on the base to fill up the trench so that the trench isolation device can be completed. The present invention is designed to solve the corner recess problem, reduce generation of kick effect, and enhance the device characteristics and electrical quality.

摘要翻译： 一种形成能够减少角凹部的沟槽隔离装置的方法，包括在半导体基底上形成衬垫氧化物层和氮化硅掩模层，并通过蚀刻形成沟槽。 接下来，在半导体基底和浅沟槽的表面上形成衬垫氧化物层。 然后，将蚀刻氮化硅掩模层以露出拐角。 最后，在基底上形成一层氧化物以填充沟槽，从而可以完成沟槽隔离装置。 本发明旨在解决拐角凹陷问题，减少踢球效应的产生，提高装置特性和电气质量。