公开(公告)号：US07671579B1

公开(公告)日：2010-03-02

申请号：US11470898

申请日：2006-09-07

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： G01R23/175 ,  G08B23/00

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US07330051B1

公开(公告)日：2008-02-12

申请号：US11354766

申请日：2006-02-14

申请人： Joseph Huang ,  Chiakang Sung ,  Michael H. M. Chu ,  Yan Chong

发明人： Joseph Huang ,  Chiakang Sung ,  Michael H. M. Chu ,  Yan Chong

IPC分类号： H03K19/173

CPC分类号： H03K19/17744

摘要： The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.

摘要翻译： 通过可编程器件的操作产生的同时开关噪声的量可以通过减少引脚数目同时减少。 I / O bank可以包括多个I / O引脚子集或DQS组，每组都被编程为在不同的时间切换，使得各个引脚的切换时间可以在每个系统时钟周期内交错。 可编程延迟元件可用于控制每个子集的延迟。 可编程元件可以放置在系统时钟和输出寄存器之间，以便延迟寄存器对时钟信号的接收，从而延迟输出缓冲器的切换。 可编程延迟元件也可以放置在输出寄存器和输出缓冲器之间，以便延迟输出缓冲器的输出数据的接收和随后的切换。

公开(公告)号：US07324405B1

公开(公告)日：2008-01-29

申请号：US11368369

申请日：2006-03-03

申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

IPC分类号： G11C8/00

CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

公开(公告)号：US06992947B1

公开(公告)日：2006-01-31

申请号：US10696209

申请日：2003-10-28

申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  G11C8/16

摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

公开(公告)号：US06731142B1

公开(公告)日：2004-05-04

申请号：US10412705

申请日：2003-04-10

申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

IPC分类号： H03K2100

CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

公开(公告)号：US06549045B1

公开(公告)日：2003-04-15

申请号：US10043620

申请日：2002-01-11

申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

IPC分类号： H03K2100

CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

公开(公告)号：US08624647B2

公开(公告)日：2014-01-07

申请号：US12690064

申请日：2010-01-19

申请人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

发明人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

摘要翻译： 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

公开(公告)号：US07990786B2

公开(公告)日：2011-08-02

申请号：US12539582

申请日：2009-08-11

申请人： Michael H. M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

发明人： Michael H. M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

公开(公告)号：US07893739B1

公开(公告)日：2011-02-22

申请号：US12549332

申请日：2009-08-27

申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058

摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的一个延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。

公开(公告)号：US07706996B2

公开(公告)日：2010-04-27

申请号：US11735394

申请日：2007-04-13

申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G06F11/00 ,  G06F19/00

CPC分类号： G06F13/4213

摘要： Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.

摘要翻译： 提供电路，方法和装置以减少由数据接口提供或发送的信号之间的偏差。 信号路径延迟是变化的，使得由存储器接口发送的信号沿着上升沿和/或下降沿彼此校准或对齐。 例如，自校准，外部电路或设计工具可以通过确定每个输出通道路径的一个或多个延迟来提供每个输出通道的偏移调整。 当对准多个边缘时，输出信号的边缘可以独立对准，例如使用边缘特定的延迟元件。