公开(公告)号：US20080197337A1

公开(公告)日：2008-08-21

申请号：US12109085

申请日：2008-04-24

Applicant: John M. Aitken ,  Fen Chen ,  Kai D. Feng

Inventor： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC: H01L47/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

Abstract: The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

Abstract translation: 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US07381981B2

公开(公告)日：2008-06-03

申请号：US11161332

申请日：2005-07-29

Applicant: John M. Aitken ,  Fen Chen ,  Kai D. Feng

Inventor： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC: H01L29/02 ,  H01L47/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

Abstract: The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

Abstract translation: 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US07129821B2

公开(公告)日：2006-10-31

申请号：US10711082

申请日：2004-08-20

Applicant: Serafino Bueti ,  Adam J. Courchesne ,  Kai D. Feng ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Scott T. Vento

Inventor： Serafino Bueti ,  Adam J. Courchesne ,  Kai D. Feng ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Scott T. Vento

IPC: G05B11/01

CPC classification number: H04B3/54 ,  H04B2203/5416

Abstract: A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.

Abstract translation: 一种通信系统，其包括具有配电网络的微电子芯片; 发射机，可操作地配置为产生通信信号并将所述通信信号提供给所述配电网络; 以及可操作地配置为从所述配电网接收所述通信信号的接收器。 还提供了一种通过微电子芯片的配电网传送通信信号的方法。

公开(公告)号：US5465143A

公开(公告)日：1995-11-07

申请号：US186966

申请日：1994-01-27

Applicant: Ching Chu ,  David Liao ,  Kai D. Feng

Inventor： Ching Chu ,  David Liao ,  Kai D. Feng

IPC: G01M11/00 ,  G01N21/88

CPC classification number: G01M11/3145

Abstract: An OTDR to examine light reflected from an optic fibre has an amplification stage that operates in either a high gain or low gain mode. To avoid saturation of the amplifier in the high gain mode, the trace is examined to identify the location of spikes and a switch is controlled to connect the amplifier to the signal after the occurrence of the spike.

Abstract translation: 检查从光纤反射的光的OTDR具有以高增益或低增益模式工作的放大级。 为了避免放大器在高增益模式下饱和，检查迹线以识别尖峰的位置，并且控制开关以在发生尖峰之后将放大器连接到信号。

公开(公告)号：US08890556B2

公开(公告)日：2014-11-18

申请号：US13282090

申请日：2011-10-26

Applicant: Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

Inventor： Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

IPC: G01R31/3187 ,  G01R31/30

CPC classification number: G01R31/3004

Abstract: An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.

Abstract translation: 用于监测电迁移（EM）性能的集成电路，测试结构和方法。 描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。

公开(公告)号：US20140035670A1

公开(公告)日：2014-02-06

申请号：US13566805

申请日：2012-08-03

Applicant: Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

Inventor： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC: H03F3/45

CPC classification number: G06F7/588 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

Abstract translation: 公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。 电路包括第一n型场效应晶体管（NFET）和第二NFET。 电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。 电路还包括闭环，其中闭环产生恒定的共模电压。

公开(公告)号：US20130241652A1

公开(公告)日：2013-09-19

申请号：US13418961

申请日：2012-03-13

Applicant: Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

Inventor： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45609 ,  H03F3/68 ,  H03F2200/408 ,  H03F2200/78

Abstract: Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

Abstract translation: 本发明的实施例提供了一种利用读出放大器来选择合适电路的方法，其中合适的电路产生大于或等于可配置参考电压的电压。 放大器增益选择器选择具有输入端，辅助输入，输出，电阻性负载阵列和放大器增益选择器的读出放大器的电压增益。 辅助输入用于消除读出放大器的直流（DC）偏移电压。 组合逻辑电路将读出放大器的输入端连接到一组电路内的电路的输出端。 比较器电路基于读出放大器的输出来确定电路是否产生大于或等于可配置参考电压的电压。

公开(公告)号：US20130233608A1

公开(公告)日：2013-09-12

申请号：US13414825

申请日：2012-03-08

Applicant: Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H05K1/11 ,  B05D5/12 ,  B05D5/00

CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

Abstract translation: 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

公开(公告)号：US08482336B2

公开(公告)日：2013-07-09

申请号：US13082434

申请日：2011-04-08

Applicant: Pinping Sun ,  Kai D. Feng ,  Essam Mina

Inventor： Pinping Sun ,  Kai D. Feng ,  Essam Mina

IPC: H03K17/687

CPC classification number: H03K17/693 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/78 ,  H03K17/6221 ,  H03K2017/066 ,  H03K2217/0018

Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

Abstract translation: 单极双掷（SPDT）半导体开关包括在发送器节点和接收节点之间的第一发送器侧晶体管和第一接收侧晶体管的串联连接。 两个第一晶体管中的每一个设置有栅极侧可变阻抗电路，其在互补的一对栅极控制信号之间提供可变阻抗连接。 此外，每个第一晶体管的主体可以通过体侧可变阻抗电路连接到体偏置控制信号。 此外，发射机节点通过第二发射机侧晶体管连接到电接地，并且接收节点通过第二接收侧晶体管连接到电接地。 每个第二晶体管可以具有连接到第一晶体管的体偏置控制信号的体偏置，使得关断晶体管提供增强的电隔离。

公开(公告)号：US08421183B2

公开(公告)日：2013-04-16

申请号：US13016126

申请日：2011-01-28

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L23/552 ,  H01L21/76 ,  H01L21/76264 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.