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    Method And Apparatus For Virtualized Microcode Sequencing
    41.
    发明申请
    Method And Apparatus For Virtualized Microcode Sequencing 审中-公开
    用于虚拟化微代码排序的方法和装置

    公开(公告)号：US20110296096A1

    公开(公告)日：2011-12-01

    申请号：US12912169

    申请日：2010-10-26

    申请人： Xiang Zou ,  Per Hammarlund ,  Ronak Singhal ,  Hong Wang

    发明人： Xiang Zou ,  Per Hammarlund ,  Ronak Singhal ,  Hong Wang

    IPC分类号： G06F12/06 ,  G06F12/08

    CPC分类号： G06F9/30174 ,  G06F9/3802 ,  G06F9/3891

    摘要： In one embodiment, the present invention includes a processor having multiple cores and an uncore. The uncore may include a microcode read only memory to store microcode to be executed in the cores (that themselves do not include such memory). The cores can include a microcode sequencer to sequence a plurality of micro-instructions (uops) of microcode that corresponds to a macro-instruction to be executed in an execution unit of the corresponding core. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有多个核心和非核心的处理器。 无孔可以包括微代码只读存储器，以存储要在核心中执行的微代码（其本身不包括这样的存储器）。 核心可以包括微代码定序器，以对应于在相应核心的执行单元中执行的宏指令的微代码的多个微指令（uop）。 描述和要求保护其他实施例。

    METHOD AND APPARATUS TO EFFICIENTLY GENERATE A PROCESSOR ARCHITECTURE MODEL
    44.
    发明申请
    METHOD AND APPARATUS TO EFFICIENTLY GENERATE A PROCESSOR ARCHITECTURE MODEL 审中-公开
    方法和设备有效地生成处理器架构模型

    公开(公告)号：US20110153529A1

    公开(公告)日：2011-06-23

    申请号：US12646541

    申请日：2009-12-23

    申请人： Anne W. Bracy ,  Mahesh Madhav ,  Hong Wang

    发明人： Anne W. Bracy ,  Mahesh Madhav ,  Hong Wang

    IPC分类号： G06F15/18 ,  G06N5/02

    CPC分类号： G06F17/5022

    摘要： A method and apparatus for efficiently generating a processor architecture model that accurately predicts performance of the processor for minimizing simulation time are described. In one embodiment, the method comprises: identifying a performance benchmark of a processor; sampling a portion of a design space for the identified performance benchmark; simulating the sampled portion of the design space to generate training data; generating a processor performance model from the training data by modifying the training data to predict an entire design space; and predicting performance of the processor for the entire design space by executing the processor performance model.

    摘要翻译： 描述了一种用于有效地生成准确地预测处理器的性能以最小化模拟时间的处理器架构模型的方法和装置。 在一个实施例中，该方法包括：识别处理器的性能基准; 对所识别的性能基准的一部分设计空间进行采样; 模拟设计空间的采样部分以产生训练数据; 通过修改训练数据来预测整个设计空间，从训练数据生成处理器性能模型; 并通过执行处理器性能模型来预测处理器对于整个设计空间的性能。

    Edge removal of silicon-on-insulator transfer wafer
    45.
    发明授权
    Edge removal of silicon-on-insulator transfer wafer 有权
    边缘去除绝缘体上硅转移晶片

    公开(公告)号：US07951718B2

    公开(公告)日：2011-05-31

    申请号：US12033727

    申请日：2008-02-19

    申请人： Raymond John Donohoe ,  Krishna Vepa ,  Paul V. Miller ,  Ronald Rayandayan ,  Hong Wang

    发明人： Raymond John Donohoe ,  Krishna Vepa ,  Paul V. Miller ,  Ronald Rayandayan ,  Hong Wang

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76254 ,  H01L21/02032 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/76251 ,  Y10S438/974

    摘要： A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant to preferentially etch away the circumferential lip, while the circular recess is masked by the spin-on-glass. The spin-on glass is removed, and the front surface of the transfer wafer is polished. Other methods of removing the circumferential lip include applying a higher pressure to the circumferential lip in a polishing process, and directing a pressurized fluid jet at the base of the circumferential lip.

    摘要翻译： 抛光具有围绕圆形凹槽的具有周向唇缘的前表面的绝缘体上硅转移晶片。 在一个版本中，通过用旋转玻璃填充凹槽来掩蔽晶片前表面上的圆形凹槽。 将晶片的前表面暴露于蚀刻剂以优先蚀刻掉周缘，同时圆形凹槽被旋涂玻璃掩蔽。 去除旋涂玻璃，并且转印晶片的前表面被抛光。 去除圆周唇缘的其它方法包括在抛光过程中向周缘施加更高的压力，并且在周向唇缘的底部引导加压流体射流。

    PORTABLE MULTI-FUNCTIONAL DATA STORAGE TRANSMITTING AND CONNECTING DEVICE
    48.
    发明申请
    PORTABLE MULTI-FUNCTIONAL DATA STORAGE TRANSMITTING AND CONNECTING DEVICE 有权
    便携式多功能数据存储传输和连接设备

    公开(公告)号：US20110065321A1

    公开(公告)日：2011-03-17

    申请号：US12736845

    申请日：2009-03-31

    申请人： Hong Wang

    发明人： Hong Wang

    IPC分类号： H01R13/66

    CPC分类号： H01R31/005 ,  H01R13/6658

    摘要： A multi-functional data storage and transmitting and connecting device for an electronic device, includes a data transfer cable having a predetermined length, at least a first and a second connector provided at two ends of the data transfer cable respectively and a coupling element. The coupling element includes a plurality of connector sockets adapted for fittedly and detachably receiving the connectors so as to detachably couple the connectors into a handy structure, a control circuitry received in the coupling element, and a hanging device. The control circuitry includes an integrated circuit chipset, a rechargeable battery provided within the coupling element for recharging the electronic device, a call receiving circuitry electrically connected with the integrated circuit chipset, a speakerphone electrically connected with sad call receiving circuitry, an amplifier adapted for amplifying audio signal, and a wireless transceiver electrically connected with the integrated circuit chipset for wirelessly receiving and transmitting signal.

    摘要翻译： 一种用于电子设备的多功能数据存储和传输和连接装置，包括具有预定长度的数据传输电缆，分别设置在数据传输电缆的两端的至少第一和第二连接器以及耦合元件。 联接元件包括多个连接器插座，其适于可装配地和可拆卸地接收连接器，从而可拆卸地将连接器连接到方便的结构中，容纳在耦合元件中的控制电路和悬挂装置。 控制电路包括集成电路芯片组，设置在耦合元件内用于对电子装置充电的可再充电电池，与集成电路芯片组电连接的呼叫接收电路，与难听的电话接收电路电连接的扬声器电话，适于放大 音频信号，以及与集成电路芯片组电连接的无线收发信号的无线收发器。

    Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration
    50.
    发明授权
    Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration 有权
    用于启用锁定竞争和加速器登记后的序列发生器通信的通信路径

    公开(公告)号：US07904696B2

    公开(公告)日：2011-03-08

    申请号：US11901178

    申请日：2007-09-14

    申请人： Perry Wang ,  Jamison Collins ,  Hong Wang

    发明人： Perry Wang ,  Jamison Collins ,  Hong Wang

    IPC分类号： G06F13/00

    CPC分类号： G06F9/30 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F15/17368 ,  G06F15/7832

    摘要： In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer via a dedicated interconnect, detecting the assertion signal in the accelerators and communicating a request for a lock on a second interconnect coupled to the first instruction sequencer and the accelerators, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer via the second interconnect. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种用于将断言信号从第一指令定序器传送到经由专用互连耦合到第一指令定序器的多个加速器的方法，检测加速器中的断言信号并传送锁定请求 在耦合到所述第一指令定序器和所述加速器的第二互连上，以及通过经由所述第二互连将所述加速器的用于所述加速器的注册消息通信到所述第一指令定序器来登记实现所述锁定的加速器。 描述和要求保护其他实施例。