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    Semiconductor memory device and method of controlling the semiconductor memory device
    41.
    发明申请
    Semiconductor memory device and method of controlling the semiconductor memory device 失效
    半导体存储器件和控制半导体存储器件的方法

    公开(公告)号：US20070237014A1

    公开(公告)日：2007-10-11

    申请号：US11806721

    申请日：2007-06-04

    申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

    摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

    摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

    Memory control device and memory control method
    42.
    发明申请
    Memory control device and memory control method 有权
    内存控制装置和内存控制方式

    公开(公告)号：US20070097776A1

    公开(公告)日：2007-05-03

    申请号：US11640906

    申请日：2006-12-19

    申请人： Yoshiharu Kato

    发明人： Yoshiharu Kato

    IPC分类号： G11C8/00

    CPC分类号： G11C5/06

    摘要： There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal SWS2. In this case, the changeover is made so that a select signal S2 outputted from an internal circuit 40 is inputted to a predetermined memory terminal of the memory chip CC2. The select signal S2 is inputted to the corresponding predetermined memory terminal of the memory chip CC2, and thereby, the memory chip CC2 is activated, and set to a state capable of inputting and outputting control signals 21 to 25. The control signals 21 to 25 are assigned to control terminals P21 to P27 after being hanged by the select circuit 27 in signal sequence corresponding to terminal array sequence of memory terminals 21a to 27a of the memory chip CC2.

    摘要翻译： 提供了存储器控制装置和存储器控制方法，可以防止多条交叉布线的布线复杂化，降低产量和质量。 当存储器控制装置CC 1选择存储器芯片CC 2时，选择电路27的内部电路被切换信号SWS2改变。在这种情况下，进行切换，使得从内部输出的选择信号S 2 电路40被输入到存储器芯片CC 2的预定存储器端子。选择信号S 2被输入到存储器芯片CC 2的对应的预定存储器端子，由此存储器芯片CC 2被激活，并被设置为 一个能够输入和输出控制信号21至25的状态。控制信号21至25被分配给控制端P21至P27，在选择电路27以对应于存储器端子21a的端子阵列序列的信号序列 到27位的内存芯片CC 2。

    Semiconductor device and method of testing the same
    43.
    发明申请
    Semiconductor device and method of testing the same 有权
    半导体器件及其测试方法

    公开(公告)号：US20070090695A1

    公开(公告)日：2007-04-26

    申请号：US11583131

    申请日：2006-10-19

    申请人： Yoshiharu Kato

    发明人： Yoshiharu Kato

    IPC分类号： H02B1/24

    CPC分类号： H03K5/26 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  Y10T307/74

    摘要： An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.

    摘要翻译： 目的是提供一种半导体器件，其中可以确定由延迟电路给出的微小延迟时间是否在规定值内，以及测试半导体器件的方法。 响应于用于测试的数据选通信号TDQS，延迟电路DC 0和DC 1产生延迟数据选通信号IDQS 0和IDQS 1延迟延迟时间DT 0和DT 1。 作为来自反相器INV 0的反向信号输出，是响应于延迟数据选通信号IDQS 0的反向数据选通信号RIDQS 0，并延迟了允许的延迟时间IT。 输入到NAND门ND 0中的是反向数据选通信号RIDQS 0和延迟数据选通信号IDQS 1。 当与延迟数据选通信号IDQS 0的相位相比，延迟数据选通信号IDQS 1的相位延迟可允许的延迟时间IT或更多时，不从NAND门ND输出脉冲信号PL 0 0。

    Memory control device and memory control method
    44.
    发明授权
    Memory control device and memory control method 有权
    内存控制装置和内存控制方式

    公开(公告)号：US07042798B2

    公开(公告)日：2006-05-09

    申请号：US10853313

    申请日：2004-05-26

    申请人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

    发明人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

    IPC分类号： G11C8/00

    CPC分类号： G06F13/4243 ,  G11C11/406 ,  Y02D10/14 ,  Y02D10/151

    摘要： It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

    摘要翻译： 旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。 在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。 此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令 被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

    Liquid crystal television and liquid crystal display apparatus
    45.
    发明申请
    Liquid crystal television and liquid crystal display apparatus 失效
    液晶电视和液晶显示装置

    公开(公告)号：US20060001782A1

    公开(公告)日：2006-01-05

    申请号：US11166395

    申请日：2005-06-23

    申请人： Yoshiharu Kato

    发明人： Yoshiharu Kato

    IPC分类号： H04N5/64

    CPC分类号： F16M11/2014 ,  F16M11/10 ,  F16M2200/08 ,  H04N5/64 ,  Y10S248/919

    摘要： There is disclosed a liquid crystal display apparatus including a main body and a swivel mechanism, where the main body is capable of smoothly swiveling. A countersunk hole is formed in a bottom plate member as follows: When a through-hole for inserting a screw is formed in a metal sheet to be a bottom plate member, there is also concurrently formed an accommodating hole for accommodating flow of the material forming the metal sheet upon plastic forming or pressing which is performed subsequently for forming a countersink, and then the countersink is formed at an open end of the through-hole by pressing. It is preferable that a plurality of the accommodating holes are formed around the through-hole.

    摘要翻译： 公开了一种包括主体和旋转机构的液晶显示装置，其中主体能够平稳地旋转。 在底板构件中形成有埋头孔，如下所述：当金属板中形成用于插入螺钉的通孔作为底板构件时，还形成有用于容纳形成材料的流动的容纳孔 金属片在塑性成形或压制时随后进行以形成埋头孔，然后通过压制在通孔的开口端形成埋头孔。 优选地，在通孔周围形成有多个容纳孔。

    Memory control device and memory control method
    48.
    发明申请
    Memory control device and memory control method 有权
    内存控制装置和内存控制方式

    公开(公告)号：US20050135177A1

    公开(公告)日：2005-06-23

    申请号：US10850113

    申请日：2004-05-21

    申请人： Yoshiharu Kato

    发明人： Yoshiharu Kato

    IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C8/00

    CPC分类号： G11C5/06

    摘要： There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal SWS2. In this case, the changeover is made so that a select signal S2 outputted from an internal circuit 40 is inputted to a predetermined memory terminal of the memory chip CC2. The select signal S2 is inputted to the corresponding predetermined memory terminal of the memory chip CC2, and thereby, the memory chip CC2 is activated, and set to a state capable of inputting and outputting control signals 21 to 25. The control signals 21 to 25 are assigned to control terminals P21 to P27 after being hanged by the select circuit 27 in signal sequence corresponding to terminal array sequence of memory terminals 21a to 27a of the memory chip CC2.

    摘要翻译： 提供了存储器控制装置和存储器控制方法，可以防止多条交叉布线的布线复杂化，降低产量和质量。 当存储器控制装置CC 1选择存储器芯片CC 2时，选择电路27的内部电路被切换信号SWS 2改变。 在这种情况下，进行切换，使得从内部电路40输出的选择信号S 2被输入到存储芯片CC 2的预定存储器端子。 选择信号S 2被输入到存储器芯片CC 2的对应的预定存储器端子，从而使存储器芯片CC 2被激活，并被设置为能够输入和输出控制信号21至25的状态。 控制信号21至25被分配给选择电路27以对应于存储器芯片CC 2的存储器端子21a至27a的端子阵列序列的信号序列挂起之后的控制端子P21至P27。

    Semiconductor device having test mode entry circuit
    49.
    发明授权
    Semiconductor device having test mode entry circuit 有权
    具有测试模式进入电路的半导体器件

    公开(公告)号：US06651196B1

    公开(公告)日：2003-11-18

    申请号：US09504795

    申请日：2000-02-15

    申请人： Akihiro Iwase ,  Yoshiharu Kato

    发明人： Akihiro Iwase ,  Yoshiharu Kato

    IPC分类号： G01R313181

    CPC分类号： G11C29/40 ,  G01R31/31701 ,  G11C11/40 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/0407

    摘要： A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

    摘要翻译： 半导体器件具有正常工作模式和测试模式。 决定电路确定设备是否进入测试模式。 当输入测试模式时，控制电路改变与正常操作模式有关的信息。 如果意外输入测试模式，则由于与正常操作有关的信息已经改变，用户可以容易地确定设备已进入测试模式。

    Drive power supplying method for semiconductor memory device and semiconductor memory device
    50.
    发明授权
    Drive power supplying method for semiconductor memory device and semiconductor memory device 有权
    半导体存储器件和半导体存储器件的驱动电源供应方法

    公开(公告)号：US06504353B2

    公开(公告)日：2003-01-07

    申请号：US09772075

    申请日：2001-01-30

    申请人： Isamu Kobayashi ,  Yoshiharu Kato

    发明人： Isamu Kobayashi ,  Yoshiharu Kato

    IPC分类号： G05F140

    CPC分类号： G05F3/242

    摘要： A drive power supply method for a semiconductor device is provided. The semiconductor device has an internal supply voltage generating circuit. First and second internal circuits are connected to the internal supply voltage generating circuit. Drive power is supplied to the first and second internal circuits from the internal supply voltage generating circuit. The second internal circuit operates in standby mode, power-down mode and active mode, so that the internal supply voltage is stably retained in the standby mode or power-down mode, and the consumed current is reduced.

    摘要翻译： 提供了一种用于半导体器件的驱动电源方法。 半导体器件具有内部电源电压发生电路。 第一和第二内部电路连接到内部电源电压发生电路。 从内部电源电压发生电路向第一和第二内部电路提供驱动电力。 第二内部电路在待机模式，掉电模式和有功模式下工作，使得内部电源电压稳定地保持在待机模式或掉电模式，并且消耗的电流降低。