公开(公告)号：US06469325B1

公开(公告)日：2002-10-22

申请号：US09297513

申请日：1999-05-03

申请人： Hiroyasu Ishizuka ,  Kousuke Okuyama ,  Katsuhiko Kubota

发明人： Hiroyasu Ishizuka ,  Kousuke Okuyama ,  Katsuhiko Kubota

IPC分类号： H01L2900

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to eliminate a difference in ESD resistance caused by the polarities of excessive voltages applied to an external terminal and enhance the ESD resistance of a semiconductor integrated circuit device to both positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.

摘要翻译： 为了消除由施加到外部端子的过大电压的极性引起的ESD电阻的差异，并且提高半导体集成电路器件的正负过电压的ESD电阻，具有可控硅结构的保护元件，用于保护 在外部端子和地电位之间设置有来自正过电压的内部电路和由用于保护内部电路免于负过电压的二极管D1构成的保护元件。

公开(公告)号：US4898840A

公开(公告)日：1990-02-06

申请号：US269702

申请日：1988-11-10

申请人： Kousuke Okuyama

发明人： Kousuke Okuyama

IPC分类号： H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A semiconductor integrated circuit device having a read-only memory which comprises a plurality of first gate electrodes arranged on a semiconductor substrate in a first direction maintaining a predetermined distance, a plurality of second gate electrodes that are arranged among said first gate electrodes and are partly overlapped on said first gate electrodes, and regions of data-writing impurities positioned under the first and second gate electrodes. The impurities for writing data are introduced through the first or second gate electrodes using the overlappings of the first and second gate electrodes as masks.

公开(公告)号：US20100136778A1

公开(公告)日：2010-06-03

申请号：US12700344

申请日：2010-02-04

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/28

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US07719052B2

公开(公告)日：2010-05-18

申请号：US12020393

申请日：2008-01-25

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US07279754B2

公开(公告)日：2007-10-09

申请号：US10465550

申请日：2003-06-20

申请人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

发明人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104

摘要： A memory cell of a SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly consist of a square pole laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。 垂直MISFET分别主要由以下顺序层叠的下半导体层，中间半导体层和上半导体层形成的方形极板层叠，形成在层叠体的侧壁表面上的氧化硅栅极绝缘膜，以及 形成为覆盖层叠体的侧壁的栅电极。 垂直MISFET是完全耗尽型MISFET。

公开(公告)号：US07067888B2

公开(公告)日：2006-06-27

申请号：US09985303

申请日：2001-11-02

申请人： Hideki Aono ,  Kousuke Okuyama ,  Kozo Watanabe ,  Kenichi Kuroda

发明人： Hideki Aono ,  Kousuke Okuyama ,  Kozo Watanabe ,  Kenichi Kuroda

IPC分类号： H01L29/772

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/105

摘要： Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effects are provided for pMIS and nMIS of inverter circuits of the next stage of an I/O buffer circuit.

摘要翻译： 对于构成I / O缓冲电路的输入第一级的反相器电路的pMIS和nMIS，不提供用于抑制短信道效应的半导体区域，而为pMIS提供用于抑制短信道效应的半导体区域 和I / O缓冲电路的下一级的反相器电路的nMIS。

公开(公告)号：US5880497A

公开(公告)日：1999-03-09

申请号：US592235

申请日：1996-01-26

申请人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

发明人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

IPC分类号： H01L27/11

CPC分类号： H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

摘要翻译： 其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。 固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。 在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

公开(公告)号：US5508540A

公开(公告)日：1996-04-16

申请号：US190596

申请日：1994-02-02

申请人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

发明人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/04 ,  H01L29/76

CPC分类号： H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

摘要翻译： 其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。 固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。 在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

公开(公告)号：US4637124A

公开(公告)日：1987-01-20

申请号：US712760

申请日：1985-03-18

申请人： Kousuke Okuyama ,  Norio Suzuki ,  Satoshi Meguro ,  Kouichi Nagasawa

发明人： Kousuke Okuyama ,  Norio Suzuki ,  Satoshi Meguro ,  Kouichi Nagasawa

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/38

CPC分类号： H01L21/823864 ,  H01L29/78

摘要： Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.

摘要翻译： 这里公开了一种制造半导体集成电路器件的方法，该半导体集成电路器件设置有N沟道和P沟道MISFET，每个N沟道和P沟道MISFET具有在其栅电极的两侧同时形成的一对侧壁间隔物。 P沟道MISFET具有通过使用栅极电极和成对侧壁间隔物作为掩模的硼离子注入形成的源极和漏极区域。 抑制具有高扩散速度的硼在栅电极下扩散。

公开(公告)号：US08652895B2

公开(公告)日：2014-02-18

申请号：US13176196

申请日：2011-07-05

申请人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

发明人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/337 ,  H01L21/8244

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104

摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。 垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的层压体，形成在层叠体的侧壁表面上的氧化硅栅极绝缘膜和栅电极 形成为覆盖层压体的侧壁。 垂直MISFET是完全耗尽型MISFET。