Network interface controller supporting network virtualization

    公开(公告)号:US20150180959A1

    公开(公告)日:2015-06-25

    申请号:US14637414

    申请日:2015-03-04

    CPC classification number: H04L67/10 G06F9/45533 H04L12/4633 H04L45/64

    Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.

    HANDLING TRANSPORT LAYER OPERATIONS RECEIVED OUT OF ORDER
    43.
    发明申请
    HANDLING TRANSPORT LAYER OPERATIONS RECEIVED OUT OF ORDER 审中-公开
    处理运输层操作接收订单

    公开(公告)号:US20150172226A1

    公开(公告)日:2015-06-18

    申请号:US14132014

    申请日:2013-12-18

    CPC classification number: H04L49/9057 G06F15/17331 H04L49/901 H04L67/1097

    Abstract: A method for communication includes receiving at a receiving node over a network from a sending node a succession of data packets belonging to a sequence of transactions, including at least one or more first packets belonging to a first transaction and one or more second packets belonging to a second transaction executed by the sending node after the first transaction, wherein at least one of the second packets is received at the receiving node before at least one of the first packets. At the receiving node, upon receipt of the data packets, data are written from the data packets in the succession to respective locations in a buffer. Execution of the second transaction at the receiving node is delayed until all of the first packets have been received and the first transaction has been executed at the receiving node.

    Abstract translation: 一种用于通信的方法包括在接收节点通过网络从发送节点接收属于事务序列的一系列数据分组,包括属于第一事务的至少一个或多个第一分组和属于第一事务的一个或多个第二分组 在所述第一事务之后由所述发送节点执行的第二事务,其中在所述第一分组中的至少一个之前在所述接收节点处接收所述第二分组中的至少一个。 在接收节点,在接收到数据分组时,将数据从连续的数据分组写入缓冲器中的相应位置。 在接收节点处的第二事务的执行被延迟,直到已经接收到所有第一个分组并且已经在接收节点处执行了第一个事务。

    Network interface controller supporting network virtualization
    44.
    发明授权
    Network interface controller supporting network virtualization 有权
    网络接口控制器支持网络虚拟化

    公开(公告)号:US09008097B2

    公开(公告)日:2015-04-14

    申请号:US13731130

    申请日:2012-12-31

    CPC classification number: H04L67/10 G06F9/45533 H04L12/4633 H04L45/64

    Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.

    Abstract translation: 网络接口设备包括用于连接到具有存储器的主机处理器的主机接口。 网络接口被配置为通过数据网络发送和接收数据分组,数据网络支持覆盖在数据网络上的多个租户网络。 处理电路被配置为经由主机接口接收由主机处理器上运行的虚拟机提交的工作项,并且响应于工作项识别虚拟机被授权通信的租户网络,其中 工作项目指定要发送到租户目标地址的消息。 处理电路响应于工作项产生包含与租户网络相关联的封装头部的数据分组,并且通过数据网络将数据分组发送到与指定的租户目的地对应的至少一个数据网络地址 地址。

    Network interface controller supporting network virtualization
    45.
    发明申请
    Network interface controller supporting network virtualization 有权
    网络接口控制器支持网络虚拟化

    公开(公告)号:US20140185616A1

    公开(公告)日:2014-07-03

    申请号:US13731130

    申请日:2012-12-31

    CPC classification number: H04L67/10 G06F9/45533 H04L12/4633 H04L45/64

    Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.

    Abstract translation: 网络接口设备包括用于连接到具有存储器的主机处理器的主机接口。 网络接口被配置为通过数据网络发送和接收数据分组,数据网络支持覆盖在数据网络上的多个租户网络。 处理电路被配置为经由主机接口接收由主机处理器上运行的虚拟机提交的工作项,并且响应于工作项识别虚拟机被授权通信的租户网络,其中 工作项目指定要发送到租户目标地址的消息。 处理电路响应于工作项产生包含与租户网络相关联的封装头部的数据分组,并且通过数据网络将数据分组发送到与指定的租户目的地对应的至少一个数据网络地址 地址。

    Sharing address translation between CPU and peripheral devices
    47.
    发明申请
    Sharing address translation between CPU and peripheral devices 有权
    共享CPU和外围设备之间的地址转换

    公开(公告)号:US20140122828A1

    公开(公告)日:2014-05-01

    申请号:US13665946

    申请日:2012-11-01

    CPC classification number: G06F12/1081

    Abstract: A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.

    Abstract translation: 一种用于存储器访问的方法包括在主机操作系统在中央处理单元(CPU)上运行的主机操作系统的控制下维护主机存储器,用于由CPU执行的多个进程的各自的地址转换表。 在外围设备中接收与给定进程相关联的工作项,在主机存储器中具有相应的地址转换表,并指定虚拟存储器地址时,外围设备将虚拟存储器地址转换为物理存储器地址 通过访问主机存储器中给定进程的相应地址转换表。 通过访问主机存储器中的物理存储器地址上的数据,在外围设备中执行工作项。

    Regrouping of video data in host memory

    公开(公告)号:US11252464B2

    公开(公告)日:2022-02-15

    申请号:US16850036

    申请日:2020-04-16

    Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

    Prioritized handling of incoming packets by a network interface controller

    公开(公告)号:US10764194B2

    公开(公告)日:2020-09-01

    申请号:US15836869

    申请日:2017-12-10

    Abstract: A network interface controller includes a host interface, which is configured to be coupled to a host processor having a host memory. A network interface is configured to receive data packets from a network, each data packet including a header, which includes header fields, and a payload including data. Packet processing circuitry is configured to process one or more of the header fields and at least a part of the data and to select, responsively at least to the one or more of the header fields, a location in the host memory. The circuitry writes the data to the selected location and upon determining that the processed data satisfies a predefined criterion, asserts an interrupt on the host processor so as to cause the host processor to read the data from the selected location in the host memory.

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