公开(公告)号：US20160269016A1

公开(公告)日：2016-09-15

申请号：US15064843

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Stephen Bowling ,  Alex Dumais

IPC: H03K7/08 ,  H02M1/08

CPC classification number: H03K7/08 ,  H02M1/08 ,  H02M3/157 ,  H02M2001/0012

Abstract: A number of standard PWM generators produce PWM signals that may be used to drive the power stages for Full-Bridge, Feed-Forward, Push-Pull, Phase-Shift Zero Voltage Transition (ZVT), and other switched mode power supply (SMPS) conversion topologies. These PWM signals may be fed to logic functions of a combinatorial logic block. Appropriate PWM signals are selected as operands along with desired logic function(s) that operates on these input operands. The resultant combinatorial PWM signals may then be used directly or may be fed through dead-time processing circuitry prior to outputting to an application circuit. In addition to the combinatorial logic functions, sequential logic functions may also be used to provide sequential PWM signals, e.g., synchronous sequential, asynchronous sequential, and/or sequential-combinatorial PWM signals.

Abstract translation: 许多标准PWM发生器产生可用于驱动全桥，前馈，推挽，相移零电压转换（ZVT）和其他开关模式电源（SMPS）的功率级的PWM信号， 转换拓扑。 这些PWM信号可以被馈送到组合逻辑块的逻辑功能。 选择适当的PWM信号作为操作数以及对这些输入操作数进行操作的所需逻辑功能。 所得到的组合PWM信号可以直接使用，或者可以在输出到应用电路之前通过死区时间处理电路馈送。 除了组合逻辑功能之外，顺序逻辑功能还可用于提供顺序PWM信号，例如同步顺序，异步顺序和/或顺序组合PWM信号。

公开(公告)号：US20160267047A1

公开(公告)日：2016-09-15

申请号：US15065027

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Igor Wojewoda ,  Alex Dumais ,  Mike Catherwood ,  Brian Fall ,  Jason Tollefson ,  Calum Wilke ,  Dave Mickey ,  Thomas Spohrer ,  Jim Pepping ,  Vincent Sheard

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/364

CPC classification number: G06F13/4282 ,  G06F1/22 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract translation: 微控制器装置具有壳体，其具有多个外部引脚，第一微控制器具有第一中央处理单元（CPU），与第一CPU耦合的第一系统总线，与第一系统总线耦合的第一存储器和第一多个外设 与第一系统总线耦合的设备，以及具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器以及与第二系统总线耦合的第二多个外围设备 第二系统总线，其中第一和第二微控制器仅通过专用接口进行通信。

公开(公告)号：US20140266833A1

公开(公告)日：2014-09-18

申请号：US14202420

申请日：2014-03-10

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Andreas Reiter ,  Tibor Futo ,  Alex Dumais

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H02M3/157 ,  H02M3/33515 ,  H03M3/502 ,  H03M7/3028 ,  H03M7/3042

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter.

Abstract translation: 坡度补偿模块使用电流模式控制提供开关模式电源的斜率补偿。 该斜率补偿功能可以由具有可选择的响应模式低通滤波器的数字斜率补偿发生器和脉冲密度调制数模转换器（PDM DAC）提供。

公开(公告)号：US20140240020A1

公开(公告)日：2014-08-28

申请号：US13778436

申请日：2013-02-27

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Bryan Kris ,  John Day ,  Alex Dumais ,  Stephen Bowling

IPC: H03K5/13

CPC classification number: H03K5/133 ,  H02M1/08 ,  H02M1/32 ,  H02M1/38 ,  H02M3/3353 ,  H02M3/33576

Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。 时间延迟电路被调整，使得每个PWM控制信号同时到达它们相关联的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设定为基本为零的延迟来实现。 此后，可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。 从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。