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    MICROELECTRONIC DEVICES AND MEMORY DEVICES
    42.
    发明申请
    MICROELECTRONIC DEVICES AND MEMORY DEVICES 有权

    公开(公告)号：US20210050357A1

    公开(公告)日：2021-02-18

    申请号：US17087419

    申请日：2020-11-02

    申请人： Micron Technology, Inc.

    发明人： Aaron S. Yip

    IPC分类号： H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11575

    摘要： A microelectronic device comprises a stack structure having tiers each including a conductive structure and an insulating structure, the stack structure comprises a staircase region comprising staircase structures, a select gate contact region, and a memory array region between the staircase region and the select gate contact region; contact structures on steps of the staircase structures; string drivers coupled to the contact structures and comprising transistors underlying and within horizontal boundaries of the staircase region; a triple well structure underlying the memory array region; a select gate structure between the stack structure and the triple well structure; semiconductive pillar structures within horizontal boundaries of the memory array region and extending through the stack structure and the select gate structure to the triple well structure; and a select gate contact structure within horizontal boundaries of the select gate contact region and extending through the stack structure to the select gate structure.

    MEMORY CELL PROGRAMMING
    44.
    发明申请
    MEMORY CELL PROGRAMMING 审中-公开

    公开(公告)号：US20190341113A1

    公开(公告)日：2019-11-07

    申请号：US16516791

    申请日：2019-07-19

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Aaron S. Yip

    IPC分类号： G11C16/10 ,  G11C11/56 ,  G11C16/26

    摘要： Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.

    ERASING MEMORY CELLS
    45.
    发明申请
    ERASING MEMORY CELLS 审中-公开

    公开(公告)号：US20190066797A1

    公开(公告)日：2019-02-28

    申请号：US15687581

    申请日：2017-08-28

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Aaron S. Yip

    IPC分类号： G11C16/14 ,  G11C16/26

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3445

    摘要： Methods include applying a first voltage to channel regions of a plurality of memory cells; applying a lower second voltage to each access line of a plurality of access lines coupled to the memory cells other than a first set of access lines; applying a lower third voltage to the first set of access lines while applying the first voltage and the second voltage; determining a desired voltage level of the third voltage for a subsequent set of access lines; and applying the third voltage to the subsequent set of access lines while applying the first voltage and while applying the second voltage to each access line of the plurality of access lines other than the subsequent set of access lines. Methods further include methods of determining the desired voltage level for the third voltage for each set of access lines.

    MEMORY CELL PROGRAMMING
    46.
    发明申请
    MEMORY CELL PROGRAMMING 审中-公开

    公开(公告)号：US20180301195A1

    公开(公告)日：2018-10-18

    申请号：US16018566

    申请日：2018-06-26

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Aaron S. Yip

    IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

    摘要： Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.

    ACCESS LINE MANAGEMENT IN A MEMORY DEVICE
    48.
    发明申请
    ACCESS LINE MANAGEMENT IN A MEMORY DEVICE 有权
    存储设备中的线路管理

    公开(公告)号：US20170076806A1

    公开(公告)日：2017-03-16

    申请号：US15342255

    申请日：2016-11-03

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

    IPC分类号： G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

    CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    摘要： Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

    摘要翻译： 存储器设备被配置为存储在对存储器设备中的特定行存储器单元执行的存储器件操作期间要应用的许多访问线偏置模式。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。