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    Reducing programming disturbance in memory devices
    42.
    发明授权
    Reducing programming disturbance in memory devices 有权

    公开(公告)号：US11342034B2

    公开(公告)日：2022-05-24

    申请号：US17157443

    申请日：2021-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10

    Abstract: Multiple apparatus and methods of the specification include a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block.

    METHODS OF FORMING MEMORY DEVICES INCLUDING STAIR STEP STRUCTURES
    43.
    发明申请
    METHODS OF FORMING MEMORY DEVICES INCLUDING STAIR STEP STRUCTURES 有权

    公开(公告)号：US20210151375A1

    公开(公告)日：2021-05-20

    申请号：US17134930

    申请日：2020-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575

    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    44.
    发明申请
    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20200321064A1

    公开(公告)日：2020-10-08

    申请号：US16784899

    申请日：2020-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/10

    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

    Memory block select circuitry including voltage bootstrapping control
    45.
    发明授权
    Memory block select circuitry including voltage bootstrapping control 有权

    公开(公告)号：US10748620B2

    公开(公告)日：2020-08-18

    申请号：US15933087

    申请日：2018-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/06 ,  G11C16/10 ,  H01L27/11529 ,  H01L27/11573 ,  G11C11/56 ,  G11C16/04

    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

    3D memory device including shared select gate connections between memory blocks
    46.
    发明授权
    3D memory device including shared select gate connections between memory blocks 有权

    公开(公告)号：US10706930B2

    公开(公告)日：2020-07-07

    申请号：US16228534

    申请日：2018-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  G11C16/26 ,  G11C16/14 ,  G11C16/08 ,  H01L27/11575

    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

    Reducing programming disturbance in memory devices
    47.
    发明授权
    Reducing programming disturbance in memory devices 有权

    公开(公告)号：US10559367B2

    公开(公告)日：2020-02-11

    申请号：US15451022

    申请日：2017-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10

    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

    MEMORY BLOCK SELECT CIRCUITRY INCLUDING VOLTAGE BOOTSTRAPPING CONTROL
    48.
    发明申请
    MEMORY BLOCK SELECT CIRCUITRY INCLUDING VOLTAGE BOOTSTRAPPING CONTROL 审中-公开

    公开(公告)号：US20190295653A1

    公开(公告)日：2019-09-26

    申请号：US15933087

    申请日：2018-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C16/10 ,  H01L27/11529 ,  H01L27/11573

    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

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