公开(公告)号：US20240071476A1

公开(公告)日：2024-02-29

申请号：US17898346

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4091

Abstract: Systems, methods, and apparatus for a memory device. In one approach, a memory device selectively enters a streaming mode when accessing memory cells in a memory array. A controller determines for new read operations whether memory cells will be accessed in a streaming mode or in a random mode. First memory cells addressed using a wordline are read by the controller. The wordline is charged to an initial voltage for reading the first memory cells. When in the streaming mode, instead of discharging the wordline after reading the first memory cells, as is done for a random mode, the controller keeps a minimum bias on the wordline and returns the wordline again to the initial voltage for performing a next read operation to read second memory cells. This saves memory device power.

公开(公告)号：US11682439B2

公开(公告)日：2023-06-20

申请号：US17381976

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Efrem Bolandrina

IPC: G11C7/22 ,  G11C8/08 ,  G06F3/06 ,  G11C11/22 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G11C8/08 ,  G06F3/0683 ,  G11C7/106 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/4085 ,  G11C11/4096

Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

公开(公告)号：US20230126944A1

公开(公告)日：2023-04-27

申请号：US17511314

申请日：2021-10-26

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Efrem Bolandrina

IPC: G11C7/10 ,  G11C8/18

Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

公开(公告)号：US20230097079A1

公开(公告)日：2023-03-30

申请号：US16976411

申请日：2020-05-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Stefan Frederik Schippers ,  Efrem Bolandrina

IPC: H01L27/24 ,  G11C13/00

Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

公开(公告)号：US11217293B2

公开(公告)日：2022-01-04

申请号：US16877161

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C11/00 ,  G11C11/22

Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

公开(公告)号：US20210020213A1

公开(公告)日：2021-01-21

申请号：US16515629

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Efrem Bolandrina

IPC: G11C8/08 ,  G06F3/06 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/22

Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

公开(公告)号：US20210012826A1

公开(公告)日：2021-01-14

申请号：US16983469

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/22 ,  G06F13/16

Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

公开(公告)号：US20200327919A1

公开(公告)日：2020-10-15

申请号：US16877161

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

公开(公告)号：US09767898B2

公开(公告)日：2017-09-19

申请号：US15210391

申请日：2016-07-14

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0033 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/79

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.

公开(公告)号：US20170047117A1

公开(公告)日：2017-02-16

申请号：US15210391

申请日：2016-07-14

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/79

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.

Abstract translation: 在一个实施例中，公开了诸如存储器件的装置。 该装置包括存储单元，数字线驱动器，存取线驱动器，钳位元件和控制电路。 存储单元和钳位元件都可以耦合到数字线。 控制电路可以被配置为使得钳位元件在一段时间内钳位数字线的电压，同时使数字线驱动器以足以使得能够选择存储器单元的电压电平将数字线偏置。 此外，当数字线的电压处于足够使得能够选择存储器单元的电压电平时，控制电路可被配置为使得存取线驱动器偏置耦合到存储单元的存取线。