公开(公告)号：US11004516B2

公开(公告)日：2021-05-11

申请号：US16897772

申请日：2020-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/26

Abstract: Apparatus including an array of memory cells comprising a plurality of strings of series-connected memory cells, a plurality of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of series-connected memory cells, and a controller configured during an erase operation of the plurality of strings of series-connected memory cells to apply a first voltage level to a node connected to an end of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells, and apply a second voltage level to a particular access line of the plurality of access lines concurrently with applying the first voltage level to the node, wherein the second voltage level has a magnitude greater than the first voltage level, and is lower than the first voltage level.

公开(公告)号：US10861555B2

公开(公告)日：2020-12-08

申请号：US16433212

申请日：2019-06-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ke Liang ,  Jun Xu

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14

Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

公开(公告)号：US10381087B2

公开(公告)日：2019-08-13

申请号：US15841107

申请日：2017-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yafeng Zhang ,  Liang Qiao ,  Chunyuan Hou ,  Jun Xu

IPC: G11C16/22 ,  G11C16/14 ,  G11C16/30

Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.

公开(公告)号：US20190066798A1

公开(公告)日：2019-02-28

申请号：US15503786

申请日：2016-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/26

Abstract: Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected memory cells, applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells, and applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first and second voltage levels, wherein the magnitude of the third voltage level is greater than the magnitude of both the first voltage level and the second voltage level, and wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the first, second and third voltage levels.

公开(公告)号：US20240071531A1

公开(公告)日：2024-02-29

申请号：US18239193

申请日：2023-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Hong-Yan Chen ,  Pamela Castalino ,  Priya Vemparala Guruswamy ,  Jun Xu ,  Gianluca Nicosia ,  Ji-Hye Gale Shin

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/12

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a target level based on a compensation value of a program command. The controller is further configured to sense a threshold voltage of the selected memory cell. The controller is further configured to in response to the compensation value having a first value and the threshold voltage being greater than a first program verify level, inhibit programming of the selected memory cell. The controller is further configured to in response to the compensation value having a second value different from the first value and the threshold voltage being greater than a second program verify level less than the first program verify level, inhibit programming of the selected memory cell.

公开(公告)号：US11862257B2

公开(公告)日：2024-01-02

申请号：US17989168

申请日：2022-11-17

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Violante Moschiano ,  Erwin E. Yu

IPC: G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10

CPC classification number: G11C16/3454 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.

公开(公告)号：US11862255B2

公开(公告)日：2024-01-02

申请号：US17666955

申请日：2022-02-08

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Theodore T. Pekny

IPC: G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/349

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

公开(公告)号：US11615846B2

公开(公告)日：2023-03-28

申请号：US17832117

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Huanyou Zhan ,  Massimo Rossini ,  Jun Xu

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G01R19/25 ,  G11C16/26

Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

公开(公告)号：US20230017995A1

公开(公告)日：2023-01-19

申请号：US17666955

申请日：2022-02-08

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Theodore T. Pekny

IPC: G06F3/06

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

公开(公告)号：US20220404408A1

公开(公告)日：2022-12-22

申请号：US17894227

申请日：2022-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G11C16/08 ,  G11C16/04 ,  G01R27/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.