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    Memory cells and methods of forming memory cells
    41.
    发明授权
    Memory cells and methods of forming memory cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US09184384B2

    公开(公告)日：2015-11-10

    申请号：US14285933

    申请日：2014-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Gurtej S. Sandhu ,  Scott E. Sills

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/16 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

    Abstract: Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 在第一导电结构上形成开口以暴露第一导电结构的上表面。 开口具有底部底部宽度。 开口具有超过底部水平的第二水平，其中第二水平具有大于底部宽度的第二宽度。 开口的底部水平填充有多部分可编程材料的第一部分，并且第二层与第一部分相衬。 衬里的第二层被多部分可编程材料的第二部分填充。 在第二部分上形成第二导电结构。 一些实施例包括存储器单元。

    MEMORY CELLS AND SEMICONDUCTOR STRUCTURES INCLUDING ELECTRODES COMPRISING A METAL, AND RELATED METHODS
    42.
    发明申请
    MEMORY CELLS AND SEMICONDUCTOR STRUCTURES INCLUDING ELECTRODES COMPRISING A METAL, AND RELATED METHODS 有权
    包含金属的电极的存储单元和半导体结构及相关方法

    公开(公告)号：US20150295171A1

    公开(公告)日：2015-10-15

    申请号：US14726779

    申请日：2015-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Dale W. Collins ,  Marko Milojevic ,  Scott E. Sills ,  Si-Young Park

    IPC: H01L45/00

    CPC classification number: H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

    Abstract: Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials.

    Abstract translation: 存储单元（例如，CBRAM单元）包括活性材料上的离子源材料和在离子源材料上的包含金属硅化物的电极。 离子源材料可以包括硫族化物材料和金属中的至少一种。 装置，例如系统和装置，包括多个这样的存储单元。 存储单元包括在离子源材料和元素金属电极之间的金属硅化物的粘附材料。 形成存储单元的方法包括形成第一电极，形成活性材料，形成离子源材料，以及在金属离子源材料上形成包括金属硅化物的第二电极。 包括铜和包括钨的材料的材料的粘合方法包括在包括铜的材料上形成硅化钨材料并处理材料。

    Memory cells with recessed electrode contacts
    43.
    发明授权
    Memory cells with recessed electrode contacts 有权
    具有凹陷电极触点的存储单元

    公开(公告)号：US09147839B2

    公开(公告)日：2015-09-29

    申请号：US14019061

    申请日：2013-09-05

    Applicant: Micron Technology Inc.

    Inventor： Scott E. Sills ,  D. V. Nirmal Ramaswamy

    IPC: H01L45/00

    CPC classification number: H01L45/1625 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/16 ,  H01L45/1683

    Abstract: Memory cells with recessed electrode contacts and methods of forming the same are provided. An example memory cell can include an electrode contact formed in a substrate. An upper surface of the electrode contact is recessed a distance relative to an upper surface of the substrate. A first portion of a memory element is formed on an upper surface of the electrode contact and the upper surface of the substrate.

    Abstract translation: 提供具有凹陷电极触点的记忆单元及其形成方法。 示例性存储单元可以包括形成在基板中的电极接触。 电极接触件的上表面相对于衬底的上表面凹入一定距离。 存储元件的第一部分形成在电极接触件的上表面和基板的上表面上。

    Memory structures, memory arrays, methods of forming memory structures and methods of forming memory arrays
    44.
    发明授权
    Memory structures, memory arrays, methods of forming memory structures and methods of forming memory arrays 有权
    存储器结构，存储器阵列，形成存储器结构的方法和形成存储器阵列的方法

    公开(公告)号：US09059403B2

    公开(公告)日：2015-06-16

    申请号：US14455298

    申请日：2014-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.

    Abstract translation: 一些实施例包括形成存储器结构的方法。 电绝缘线形成在基底上。 电极材料沉积在线上并被图案化以沿着线的侧壁形成一对底部电极。 可编程材料形成在底部电极上，顶部电极形成在可编程材料上。 底部电极可以各自包含至少一个相对于基底的平面形状以大于0°至小于或等于约90°的角度延伸的部分。 一些实施例包括具有从导电接触向可编程材料向上延伸的底部电极的存储器结构，底部电极具有小于或等于约10纳米的厚度。 一些实施例包括存储器阵列和形成存储器阵列的方法。

    Resistive memory sensing
    45.
    发明授权
    Resistive memory sensing 有权
    电阻式记忆感测

    公开(公告)号：US09058875B2

    公开(公告)日：2015-06-16

    申请号：US13921951

    申请日：2013-06-19

    Applicant: Micron Technology, Inc.

    Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

    Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

    Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。

    METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS AND METHODS OF FORMING SEMICONDUCTOR DEVICES
    46.
    发明申请
    METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS AND METHODS OF FORMING SEMICONDUCTOR DEVICES 有权
    选择性聚合材料的方法和形成半导体器件的方法

    公开(公告)号：US20150140777A1

    公开(公告)日：2015-05-21

    申请号：US14607329

    申请日：2015-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Jerome A. Imonigie ,  Prashant Raghu ,  Theodore M. Taylor ,  Scott E. Sills

    IPC: H01L45/00

    CPC classification number: H01L45/1658 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641

    Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide.

    Abstract translation: 选择性地形成金属掺杂的硫族化物材料的方法包括将硫族化物材料暴露于过渡金属溶液，并将过渡溶液的过渡金属掺入硫族化物材料中，而基本上不将过渡金属掺入相邻的材料中。 硫族化物材料不是硒化银。 另一种方法包括形成与绝缘材料相邻并与其接触的硫族化物材料，将硫族化物材料和绝缘材料暴露于过渡金属溶液，并将过渡金属溶液的过渡金属扩散到硫族化物材料中，同时基本上没有过渡金属扩散 进入绝缘材料。 还公开了一种使用至少一种过渡金属掺杂存储单元的硫族化物材料而不使用蚀刻或化学机械平坦化工艺以从存储器单元的绝缘材料除去过渡金属的方法，其中硫族化物材料不是银 硒化物

    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES
    48.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES 有权
    形成半导体器件结构的方法和相关半导体器件结构

    公开(公告)号：US20150076436A1

    公开(公告)日：2015-03-19

    申请号：US14546897

    申请日：2014-11-18

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Dan B. Millward

    IPC: H01L45/00

    CPC classification number: H01L45/1266 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1658 ,  H01L45/1683

    Abstract: A method of forming a semiconductor device structure. The method comprises forming a block copolymer assembly comprising at least two different domains over an electrode. At least one metal precursor is selectively coupled to the block copolymer assembly to form a metal-complexed block copolymer assembly comprising at least one metal-complexed domain and at least one non-metal-complexed domain. The metal-complexed block copolymer assembly is annealed in to form at least one metal structure. Other methods of forming a semiconductor device structures are described. Semiconductor device structures are also described.

    Abstract translation: 一种形成半导体器件结构的方法。 该方法包括在电极上形成包含至少两个不同结构域的嵌段共聚物组合物。 选择性地将至少一种金属前体偶联到嵌段共聚物组合物上以形成包含至少一个金属络合域和至少一个非金属络合域的金属络合嵌段共聚物组合物。 将金属络合的嵌段共聚物组合物退火以形成至少一种金属结构。 描述形成半导体器件结构的其它方法。 还描述了半导体器件结构。

    THREE DIMENSIONAL MEMORY ARRAY WITH SELECT DEVICE
    49.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY WITH SELECT DEVICE 有权
    三维存储器与选择器件阵列

    公开(公告)号：US20140361239A1

    公开(公告)日：2014-12-11

    申请号：US13915302

    申请日：2013-06-11

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy ,  Scott E. Sills ,  Gurtej S. Sandhu

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/11578 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

    Abstract: Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

    Abstract translation: 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部， 至少一个导电延伸部与多个第一导电线中的每一个相交。 存储元件材料布置在至少一个导电延伸部周围，并且选择装置围绕存储元件材料布置。 存储元件材料与分离多个第一导电线的绝缘材料径向相邻，并且围绕存储元件材料布置的多个材料径向地邻近多个第一导电线中的每一个。

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