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    Memory cells, memory systems, and memory programming methods
    2.
    发明授权
    Memory cells, memory systems, and memory programming methods 有权

    公开(公告)号：US10395731B2

    公开(公告)日：2019-08-27

    申请号：US15858201

    申请日：2017-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino ,  D. V. Nirmal Ramaswamy

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

    Memory cells, memory systems, and memory programming methods
    6.
    发明授权
    Memory cells, memory systems, and memory programming methods 有权
    存储单元，存储器系统和存储器编程方法

    公开(公告)号：US09293196B2

    公开(公告)日：2016-03-22

    申请号：US13837911

    申请日：2013-03-15

    Applicant: Micron Technology, Inc.

    Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitigawa ,  Jun Sumino ,  D. V. Nirmal Ramaswamy

    IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00

    CPC classification number: G11C13/0002 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146

    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

    Abstract translation: 描述了存储器单元，存储器系统和方法。 在一个实施例中，存储单元包括电极和存储元件，并且第一导电结构形成在电介质材料内，由于施加在电极上的第一极性的第一电压，从而提供低电阻状态的存储元件 。 另外，由于与第一极性相反的第二极性的第二电压被施加在电极两端，所以第一导电结构从提供存储元件的电介质材料中移除到高电阻状态。 作为第二极性的第三电压的结果，在提供存储元件处于低电阻状态的电介质材料中形成永久且不可逆的导电结构，并且与施加在电极上的第二电压相比具有增加的电位。

    Apparatuses having a ferroelectric field-effect transistor memory array and related method
    7.
    发明授权
    Apparatuses having a ferroelectric field-effect transistor memory array and related method 有权
    具有铁电场效应晶体管存储器阵列和相关方法的装置

    公开(公告)号：US09281044B2

    公开(公告)日：2016-03-08

    申请号：US13897037

    申请日：2013-05-17

    Applicant: Micron Technology, Inc.

    Inventor： D. V. Nirmal Ramaswamy ,  Adam D. Johnson

    IPC: G11C11/22

    CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

    Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

    Abstract translation: 一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。 在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。 另一种装置包括多个位线和字线。 每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻的栅极共享以使多个FeFET发生。 操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元。

    Memory cells and methods of forming memory cells
    8.
    发明授权
    Memory cells and methods of forming memory cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US09153776B2

    公开(公告)日：2015-10-06

    申请号：US14070374

    申请日：2013-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Martin Schubert ,  Scott E. Sills ,  D. V. Nirmal Ramaswamy

    IPC: H01L45/00

    CPC classification number: H01L45/1266 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608

    Abstract: Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a first metal and a second metal. The switching material is a second composition which includes the second metal. The second composition is directly against the first composition. Some embodiments include methods of forming memory cells.

    Abstract translation: 一些实施例包括在电极上方具有电极和开关材料的存储单元。 电极是包括第一金属和第二金属的第一组合物。 开关材料是包括第二金属的第二组合物。 第二组合物直接抵抗第一组合物。 一些实施例包括形成存储器单元的方法。

    Nonvolatile memory cells and methods of forming nonvolatile memory cells
    9.
    发明授权
    Nonvolatile memory cells and methods of forming nonvolatile memory cells 有权
    非易失性存储单元和形成非易失性存储单元的方法

    公开(公告)号：US09117998B2

    公开(公告)日：2015-08-25

    申请号：US14319290

    申请日：2014-06-30

    Applicant: Micron Technology, Inc.

    Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

    IPC: H01L45/00

    CPC classification number: H01L45/085 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

    Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed.

    Abstract translation: 形成非易失性存储单元的方法包括形成具有第一电流导电材料的第一电极和从第一电流导电材料向外突出的周向自对准的第二导电材料。 第二电流导电材料的组成与第一电流导电材料不同。 可编程区域形成在第一电流导电材料之上并且在第一电极的突出的第二电流导电材料之上。 在可编程区域上形成第二电极。 在一个实施例中，可编程区域是离子传导材料，并且第一和第二电极中的至少一个电极具有直接抵靠离子导电材料的电化学活性表面。 公开了其它方法和结构方面。

    Electronic devices, memory devices and memory arrays
    10.
    发明授权
    Electronic devices, memory devices and memory arrays 有权
    电子设备，存储设备和存储器阵列

    公开(公告)号：US08976566B2

    公开(公告)日：2015-03-10

    申请号：US13710785

    申请日：2012-12-11

    Applicant: Micron Technology, Inc.

    Inventor： D. V. Nirmal Ramaswamy ,  Kirk D. Prall

    IPC: G11C11/00 ,  G11C11/34 ,  H01L27/105 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/14 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

    Abstract: Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

    Abstract translation: 一些实施例包括具有串联连接的两个电容器的电子设备。 两个电容器共享一个公共电极。 电容器中的一个包括半导体衬底的区域和这种区域与公共电极之间的电介质。 电容器中的另一个包括在第二电极和公共电极之间的第二电极和离子传导材料。 第一和第二电极中的至少一个具有直接抵靠离子导电材料的电化学活性表面。 一些实施例包括具有串联连接的两个电容器的存储器单元，并且一些实施例包括包含这种存储器单元的存储器阵列。

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