公开(公告)号：US20140347929A1

公开(公告)日：2014-11-27

申请号：US14332982

申请日：2014-07-16

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/08 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates.

Abstract translation: 提供了用于转置选择门的装置和方法，诸如在计算系统和/或存储装置中。 一个示例性设备可以包括一组存储器单元和电耦合到该组存储器单元的选择栅极。 选择栅极被布置成使得一对选择栅极沿着该对选择栅极中的每一个的第一部分彼此相邻并且沿着该对选择栅极中的每一个的第二部分不相邻。

公开(公告)号：US20140347926A1

公开(公告)日：2014-11-27

申请号：US14451208

申请日：2014-08-04

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  G11C16/04

CPC classification number: G11C5/06 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor.

公开(公告)号：US20140313828A1

公开(公告)日：2014-10-23

申请号：US13864733

申请日：2013-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/28

Abstract: A memory device, system, and method for operation of a memory device are disclosed. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of drain select devices are coupled to each string of memory cells. An upper drain select device shares common support circuitry (e.g., selecting/deselecting transistors) with one or more upper drain select devices of other strings of memory cells. The support circuitry (e.g., selecting/deselecting transistors) for lower drain select devices can also be shared between a plurality of strings of memory cells.

Abstract translation: 公开了一种用于存储器件操作的存储器件，系统和方法。 在一个这样的存储器件中，存储器件包括多个存储器单元串。 多个漏极选择装置耦合到每个存储单元串。 上漏极选择装置与其他存储器单元串的一个或多个上漏极选择装置共享公共支撑电路（例如，选择/取消选择晶体管）。 用于下排流选择器件的支持电路（例如，选择/取消选择晶体管）也可以在多个存储单元串之间共享。

公开(公告)号：US20140198586A1

公开(公告)日：2014-07-17

申请号：US14216528

申请日：2014-03-17

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C5/143 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.

Abstract translation: 描述包括使能电路的设备和系统的示例。 可以使用两个电压源来操作设备的不同部分，包括外围电路和I / O电路。 当一个或多个器件的外围电路的电源被禁止时，该器件的I / O电路可能被禁止。 在一些示例中，可以通过消除或减少通过I / O电路的DC电流路径来部分地节省功率。

公开(公告)号：US20140098611A1

公开(公告)日：2014-04-10

申请号：US14103560

申请日：2013-12-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/10

Abstract: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state.

Abstract translation: 提供了实施例，其包括存储器系统，其包括存储器系统，其具有耦合在全局线路和本地线路之间的接入设备和耦合到全局线路的电压源，并且被配置为当存储器在全局线路上输出偏置电压 系统处于非操作状态。 当存储器系统处于非操作状态时，选择访问设备，并且当存储器系统处于其他状态时，访问设备被取消选择。 另外的实施例提供了一种方法，其包括将全局访问线耦合到本地访问线路，在存储器设备处于第一状态时将本地访问线路偏压到不同于负电源电压的电压，并且解除全局访问 当存储器设备处于另一状态时，从本地访问线路线。

公开(公告)号：US11600631B2

公开(公告)日：2023-03-07

申请号：US16937166

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

公开(公告)号：US11462277B2

公开(公告)日：2022-10-04

申请号：US17245275

申请日：2021-04-30

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

公开(公告)号：US11347401B2

公开(公告)日：2022-05-31

申请号：US17157272

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/00 ,  H01L29/51 ,  H01L27/1159 ,  H01L27/11597

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

公开(公告)号：US11276437B2

公开(公告)日：2022-03-15

申请号：US16921206

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11529 ,  G11C16/26 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22 ,  G11C16/16 ,  G11C16/08

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US10964400B2

公开(公告)日：2021-03-30

申请号：US16800530

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.