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公开(公告)号：US20240145010A1
公开(公告)日：2024-05-02
申请号：US18404827
申请日：2024-01-04
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C16/3481
Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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公开(公告)号：US11961581B2
公开(公告)日：2024-04-16
申请号：US17499218
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo
CPC classification number: G11C7/1006 , G11C7/1096 , G11C8/12 , G11C16/08 , G11C19/32 , H10B41/35 , H10B43/27 , G11C11/5621
Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.
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公开(公告)号：US11569255B2
公开(公告)日：2023-01-31
申请号：US17314384
申请日：2021-05-07
Applicant: Micron Technology, Inc.
Inventor： Chris M. Carlson , Ugo Russo
IPC: H01L27/1157 , H01L21/28 , H01L27/11582 , H01L29/423 , H01L29/51
Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US11170826B2
公开(公告)日：2021-11-09
申请号：US16810058
申请日：2020-03-05
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo
IPC: G11C16/00 , G11C7/10 , G11C19/32 , H01L27/11524 , H01L27/11582 , G11C8/12 , G11C16/08 , G11C11/56
Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.
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公开(公告)号：US20210265365A1
公开(公告)日：2021-08-26
申请号：US17314384
申请日：2021-05-07
Applicant: Micron Technology, Inc.
Inventor： Chris M. Carlson , Ugo Russo
IPC: H01L27/1157 , H01L27/11582 , H01L29/51 , H01L29/423 , H01L21/28
Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.
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Patent Agency Ranking
公开(公告)号：US10460798B2
公开(公告)日：2019-10-29
申请号：US16158353
申请日：2018-10-12
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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公开(公告)号：US10128315B2
公开(公告)日：2018-11-13
申请号：US15487743
申请日：2017-04-14
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Giorgio Servalli
Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
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公开(公告)号：US10102905B2
公开(公告)日：2018-10-16
申请号：US15617381
申请日：2017-06-08
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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公开(公告)号：US09627440B2
公开(公告)日：2017-04-18
申请号：US14285286
申请日：2014-05-22
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Giorgio Servalli
CPC classification number: H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1608
Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
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公开(公告)号：US20160365142A1
公开(公告)日：2016-12-15
申请号：US15245249
申请日：2016-08-24
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C11/5678 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/008 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/16
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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