公开(公告)号：US11177202B2

公开(公告)日：2021-11-16

申请号：US16680636

申请日：2019-11-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/538

Abstract: A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.

公开(公告)号：US20180308748A1

公开(公告)日：2018-10-25

申请号：US15490946

申请日：2017-04-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/2481 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/28 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A 3D stacking semiconductor device and a manufacturing method thereof are provided. The method includes using a set of N etch masks for creating O different numbers of removed layers in the conductive layers and the insulating layers for forming landing areas on the conductive layers in the contact region, each mask including mask and etch regions, N being an integer equal to or larger than 2, O being an integer larger than 2, 2N-1

公开(公告)号：US20180174955A1

公开(公告)日：2018-06-21

申请号：US15382969

申请日：2016-12-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532 ,  H01L49/02 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11575 ,  H01L28/60

Abstract: A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a substrate, and the stack includes a multi-layer area and a contact area adjacent to the multi-layer area. Next, a plurality of first openings are formed in the contact area. Then, a conductive connecting structure is formed on the stack and into the first openings. Thereafter, the stack is patterned. The conductive connecting structure continuously extends on the contact area and into the first openings to maintain an electrical connection among the conductive layers while the stack is patterned.

公开(公告)号：US09922877B2

公开(公告)日：2018-03-20

申请号：US14826257

申请日：2015-08-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/52 ,  H01L21/768 ,  H01L27/11582

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L27/11582 ,  H01L28/00

Abstract: A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive connecting element disposed on the substrate. The conductive connecting element comprises a connecting part and an extending part. The connecting part has a bottom portion electrically contacting with the conductive layer. The extending part laterally extends outwards from a top portion of the connecting part, and the extending part and the connecting part are respectively formed of different materials.

公开(公告)号：US09876055B1

公开(公告)日：2018-01-23

申请号：US15367390

申请日：2016-12-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1683

Abstract: A three-dimensional semiconductor device includes a multi-layered stack structure with memory layers parallel to each other and separated by interlayer insulation layers; and memory cell structures formed at each memory layer by arranging in a multi-row and multi-column array. One memory cell structure includes a memory material layer; a selector layer formed at an outer surface of the memory material layer and connected to the memory material layer; a first electrode layer formed at an outer surface of the selector layer and electrically connected to the selector layer; and a second electrode layer formed at an inner surface of the memory material layer and connected to the memory material layer, wherein the second electrode layer penetrates the multi-layered stack structure. Each memory layer includes a conductive layer electrically connecting the first electrode layer and the conductive layer electrically connects the adjacent memory cell structures.

公开(公告)号：US09870835B2

公开(公告)日：2018-01-16

申请号：US14637476

申请日：2015-03-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G11C29/00 ,  G11C29/44 ,  G06F11/10 ,  G11C29/52 ,  G11C29/56

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/76 ,  G11C2029/5604

Abstract: A memory repairing method and a memory device applying the same are disclosed, wherein the method comprises steps as follows: A memory device comprising at least one page having a plurality of cell strings is firstly provided. A regular data pattern is then provided to block at least two of the plurality of cell strings, and the blocked cells strings are marked as inaccessible.

公开(公告)号：US20170294384A1

公开(公告)日：2017-10-12

申请号：US15096315

申请日：2016-04-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L23/5283 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11556 ,  H01L27/11582 ,  H01L28/00

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer, and a conductive structure. The stack structure includes a plurality of conductive layers and a plurality of insulating layers stacked interlacedly. The etching stop layer is formed on a sidewall of the stack structure. An energy gap of the etching stop layer is larger than 6 eV. The conductive structure is electrically connected to at least one of the conductive layers.

公开(公告)号：US09679849B1

公开(公告)日：2017-06-13

申请号：US15096785

申请日：2016-04-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L23/528 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76816 ,  G11C16/0483 ,  G11C16/3427 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/11582

Abstract: Area overhead is reduced between adjacent blocks of a 3D vertical channel memory device. In various embodiments, vertically oriented pillars that intersect layers of string select lines and word lines are arranged at intersections of a regular grid that is rotated, in a “twisted” array of pillars. Sides of shapes of the 3D NAND array structure are undulating, and follow undulating lines in which the outer pillars are disposed. For example, any of the string select lines, word lines, ground select lines, and ground lines have sides with undulating shapes.

公开(公告)号：US20170092632A1

公开(公告)日：2017-03-30

申请号：US14865034

申请日：2015-09-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L25/18 ,  G11C16/08 ,  H01L23/528 ,  H01L27/115 ,  G11C16/24

CPC classification number: H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory structure is provided. The memory structure includes a first chip. The first chip has an array region and a periphery region. The first chip includes a first stack and a plurality of through structures. The first stack is disposed in the periphery region. The first stack includes alternately stacked conductive layers and insulating layers. The through structures each include an opening, a dielectric layer and a channel material. The opening is through the first stack. The dielectric layer is disposed on a sidewall of the opening. The channel material is disposed in the opening, and the channel material covers the dielectric layer.

公开(公告)号：US20170084310A1

公开(公告)日：2017-03-23

申请号：US15364291

申请日：2016-11-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G11C5/02 ,  H01L27/11565 ,  G11C8/08 ,  G11C5/06 ,  G11C7/10 ,  G11C8/10 ,  H01L27/11519 ,  H01L23/528

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=1/5 to 1/2. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=1/2 or 1.