公开(公告)号：US06737977B2

公开(公告)日：2004-05-18

申请号：US10040629

申请日：2002-01-09

申请人： Takayuki Nishikawa ,  Shoichi Oka ,  Koji Sakamoto ,  Takeshi Wada ,  Yasuyuki Kawano ,  Kenji Toyoda ,  Naoya Nagasawa ,  Shinji Kirihata

发明人： Takayuki Nishikawa ,  Shoichi Oka ,  Koji Sakamoto ,  Takeshi Wada ,  Yasuyuki Kawano ,  Kenji Toyoda ,  Naoya Nagasawa ,  Shinji Kirihata

IPC分类号： G08B1710

CPC分类号： G08B17/06 ,  G08B17/107 ,  G08B17/113 ,  G08B29/183

摘要： An improved fire detector unit has a plastic base defining a smoke chamber for detection of a smoke density in terms of light scattering due to the smoke particles in the smoke chamber. The base carries a circuit board mounting a light emitting element, a light receiving element, and other components forming a fire detecting circuit responsible for generating a fire warning signal based upon the detected smoke density. A metal-made electromagnetic shield is molded into the base to protect the light receiving element from electromagnetic radiation noises. The electromagnetic shield includes a ground terminal for connection with a ground line of the circuit board. In addition, terminal pins are molded into the base for electrical and physical connection of the circuit board to the base.

摘要翻译： 改进的火灾探测器单元具有限定烟室的塑料基座，用于根据烟雾室中的烟雾颗粒在光散射方面检测烟雾浓度。 底座承载安装发光元件的电路板，光接收元件和形成火灾检测电路的其他部件，该电路负责基于检测到的烟雾浓度产生火警警告信号。 金属制的电磁屏蔽件被模制到基座中以保护光接收元件免受电磁辐射噪声。 电磁屏蔽包括用于与电路板的接地线连接的接地端子。 此外，端子销被模制到基座中，用于将电路板与基座的电气和物理连接。

公开(公告)号：US06680810B2

公开(公告)日：2004-01-20

申请号：US09733088

申请日：2000-12-11

申请人： Masashi Shiraishi ,  Takeshi Wada ,  Takashi Honda ,  Haruyuki Morita ,  Mitsuyoshi Kawai ,  Norikazu Ota

发明人： Masashi Shiraishi ,  Takeshi Wada ,  Takashi Honda ,  Haruyuki Morita ,  Mitsuyoshi Kawai ,  Norikazu Ota

IPC分类号： G11B2102

CPC分类号： G11B5/012 ,  G11B5/3106 ,  G11B5/4853 ,  G11B5/486 ,  G11B5/5552 ,  G11B21/025 ,  G11B33/121

摘要： A HSA includes a magnetic head slider with at least one thin-film magnetic head element, an actuator fixed to the magnetic head slider for performing precise positioning of the at least one thin-film magnetic head element, an IC chip having a first circuit for the thin-film magnetic head element and a second circuit for driving the actuator, and a suspension for supporting the actuator and the IC chip.

摘要翻译： HSA包括具有至少一个薄膜磁头元件的磁头滑动器，固定到磁头滑动器的致动器，用于执行至少一个薄膜磁头元件的精确定位; IC芯片，具有第一电路 薄膜磁头元件和用于驱动致动器的第二电路，以及用于支撑致动器和IC芯片的悬架。

公开(公告)号：USD466487S1

公开(公告)日：2002-12-03

申请号：US29158964

申请日：2002-04-15

申请人： Takeshi Wada ,  Hiromi Chida

设计人： Takeshi Wada ,  Hiromi Chida

公开(公告)号：US5973964A

公开(公告)日：1999-10-26

申请号：US182630

申请日：1998-10-30

申请人： Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

发明人： Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

IPC分类号： G06F3/06 ,  G06F11/14 ,  G06F12/08 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/765 ,  G06F11/1433 ,  G06F11/1441 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0866 ,  G06F3/0601 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/068 ,  G11C29/789 ,  G11C29/82 ,  G06F2003/0694 ,  G06F2212/2022 ,  G06F2212/312

摘要： A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

公开(公告)号：US5862083A

公开(公告)日：1999-01-19

申请号：US640998

申请日：1996-04-30

申请人： Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

发明人： Tsunehiro Tobita ,  Jun Kitahara ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Ryuichi Hattori ,  Yukihiro Seki ,  Hajime Yamagami ,  Takashi Totsuka ,  Takeshi Wada ,  Yosio Takaya ,  Manabu Saito ,  Kenichi Kaki ,  Takao Okubo ,  Takashi Kikuchi ,  Masamichi Kishi ,  Takeshi Suzuki ,  Shigeru Kadowaki

IPC分类号： G06F3/06 ,  G06F11/14 ,  G06F12/08 ,  G11C29/00 ,  G11C16/06

CPC分类号： G11C29/765 ,  G06F11/1433 ,  G06F11/1441 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0866 ,  G06F3/0601 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/068 ,  G11C29/789 ,  G11C29/82 ,  G06F2003/0694 ,  G06F2212/2022 ,  G06F2212/312

摘要： A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

摘要翻译： 当闪存用作信息处理系统中的半导体盘或主存储器时的控制方法和系统。 半导体文件系统包括电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制存储器的控制器和控制控制器的控制部分，其中对应于由 访问一个外部系统。 第一非易失性存储器存储用于执行操作的外部系统的数据，指示存储数据的物理地址与逻辑地址之间的对应关系的第一管理信息，以及指示第一非易失性存储器的状态的第二管理信息。 第二非易失性存储器预先存储从外部系统输入和输出数据所需的接口信息以及数据的只读数据。 控制器包括控制装置，用于当数据从第一非易失性存储器输出时或当数据被输入到易失性存储器时，确定形成物理地址的预定高位的物理扇区地址，存储确定的物理扇区地址的装置，以及 用于连续地产生由物理扇区地址确定的扇区中的地址的装置。

公开(公告)号：US5844842A

公开(公告)日：1998-12-01

申请号：US249899

申请日：1994-05-26

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

公开(公告)号：US5773010A

公开(公告)日：1998-06-30

申请号：US564395

申请日：1995-11-29

申请人： Satoru Oka ,  Kazuhisa Ono ,  Seiko Shigeta ,  Takeshi Wada

发明人： Satoru Oka ,  Kazuhisa Ono ,  Seiko Shigeta ,  Takeshi Wada

IPC分类号： A61K39/35 ,  A61K38/00 ,  A61K49/00 ,  A61P37/08 ,  C07K1/14 ,  C07K14/00 ,  C07K14/435 ,  G01N33/53 ,  A61B8/00 ,  C12Q1/00

CPC分类号： C07K14/43531 ,  A61K38/00

摘要： New purified mite allergens useful as pharmaceutical and diagnostic compositions for the treatment and diagnosis of mite allergic diseases are provided. Both allergens are contained in fecal extracts of mites in culture. The high molecular weight allergen has a weight average molecular weight of 70,000 to 80,000 as determined by sedimentation equilibrium. This is a glycoprotein containing more than about 70% sugar, and possesses allergen activity. The low molecular weight antigen has a molecular weight of 1,500 to 5,000 as determined by Sephadex G25 gel filtration. This is a glycoprotein containing more than about 40% sugar, and also possesses allergen activity.

摘要翻译： 提供了用作治疗和诊断螨过敏性疾病的药物和诊断组合物的新的纯化螨过敏原。 两种过敏原都包含在文化中螨的粪便提取物中。 高分子量变应原具有通过沉降平衡测定的重均分子量为70,000至80,000。 这是含有超过约70％糖的糖蛋白，具有过敏原活性。 通过Sephadex G25凝胶过滤测定，低分子量抗原的分子量为1,500至5,000。 这是一种含有超过约40％糖的糖蛋白，也具有过敏原活性。

公开(公告)号：US5496554A

公开(公告)日：1996-03-05

申请号：US283905

申请日：1994-08-04

申请人： Satoru Oka ,  Kazuhisa Ono ,  Seiko Shigeta ,  Takeshi Wada

发明人： Satoru Oka ,  Kazuhisa Ono ,  Seiko Shigeta ,  Takeshi Wada

IPC分类号： A61K39/35 ,  A61K38/00 ,  A61K49/00 ,  A61P37/08 ,  C07K1/14 ,  C07K14/00 ,  C07K14/435 ,  G01N33/53

CPC分类号： C07K14/43531 ,  A61K38/00

摘要： New purified mite allergens useful as pharmaceutical and diagnostic compositions for the treatment and diagnosis of mite allergic diseases are provided. Both allergens are contained in fecal extracts of mites in culture. The high molecular weight allergen has a weight average molecular weight of 70,000 to 80,000 as determined by sedimentation equilibrium. This is a glycoprotein containing more than about 70% sugar, and possesses allergen activity. The low molecular weight antigen has a molecular weight of 1,500 to 5,000 as determined by Sephadex G25 gel filtration. This is a glycoprotein containing more than about 40% sugar, and also possesses allergen activity.

摘要翻译： 提供了用作治疗和诊断螨过敏性疾病的药物和诊断组合物的新的纯化螨过敏原。 两种过敏原都包含在文化中螨的粪便提取物中。 高分子量变应原具有通过沉降平衡测定的重均分子量为70,000至80,000。 这是含有超过约70％糖的糖蛋白，具有过敏原活性。 通过Sephadex G25凝胶过滤测定，低分子量抗原的分子量为1,500至5,000。 这是一种含有超过约40％糖的糖蛋白，也具有过敏原活性。

公开(公告)号：US4972371A

公开(公告)日：1990-11-20

申请号：US203456

申请日：1988-06-07

申请人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

发明人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/7884

摘要： An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

摘要翻译： 一种EEPROM，其中存储单元由浮置栅电极，控制栅极电极，设置在半导体衬底的主表面部分中的与数据线连接的栅电极的端侧上的第一半导体区域构成， 以及第二半导体区域，设置在与所述接地线连接的所述栅电极的相对端侧的所述半导体衬底的不同主表面部分中。 漏极的使用方式取决于写入数据的操作，读取数据和擦除数据。 选择第一半导体区域中的杂质浓度低于第二半导体区域的杂质浓度，以提高写入和擦除特性以及增加读取速度。

公开(公告)号：US4626395A

公开(公告)日：1986-12-02

申请号：US753241

申请日：1985-07-09

申请人： Takeshi Wada ,  Hiroshi Nakamura ,  Masami Fukui ,  Nobutatsu Yamaoka

发明人： Takeshi Wada ,  Hiroshi Nakamura ,  Masami Fukui ,  Nobutatsu Yamaoka

IPC分类号： C04B35/46 ,  C04B35/01 ,  C04B35/468 ,  H01B3/12 ,  H01G4/12 ,  H01G4/232 ,  C04B40/00 ,  H01G4/10

CPC分类号： H01G4/2325 ,  C04B35/4682 ,  H01G4/1227

摘要： A ceramic composition capable of sintering at a sufficiently low temperature to enable the use of a low cost base metal as the electrode material in the fabrication of capacitors. The major ingredient of the composition is expressed as Ba.sub.k-x M.sub.x O.sub.k TiO.sub.2, where M is one or more of magnesium, zinc, strontium, and calcium, and where k, and x are numerals in the ranges of 1.00 to 1.04, and 0.02 to 0.05, respectively. To this major ingredient is added a minor proportion of a mixture of boron oxide and at least one of barium oxide, magnesium oxide, zinc oxide, strontium oxide, and calcium oxide. For the fabrication of coherently bonded bodies of this composition, as for use as the dielectric bodies of capacitors, the moldings of the mixture of the major ingredient and additive in finely divided form are sintered in a reductive or neutral atmosphere and then reheated at a lower temperature in an oxidative atmosphere. The sintering temperature can be so low (typically from 1050.degree. to 1200.degree. C.) that the moldings can be co-sintered with base metal electrodes buried therein without difficulties encountered heretofore.