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188 条记录 (耗时 0.046 秒)

    Stacked multi-gate transistor design and method of fabrication
    42.
    发明申请
    Stacked multi-gate transistor design and method of fabrication 有权
    堆叠多栅晶体管的设计与制作方法

    公开(公告)号：US20070231997A1

    公开(公告)日：2007-10-04

    申请号：US11395860

    申请日：2006-03-31

    申请人： Brian Doyle ,  Titash Rakshit ,  Robert Chau ,  Suman Datta ,  Justin Brask ,  Uday Shah

    发明人： Brian Doyle ,  Titash Rakshit ,  Robert Chau ,  Suman Datta ,  Justin Brask ,  Uday Shah

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/7853 ,  H01L29/66818

    摘要： A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a narrow section, each pair being located at a different height of the silicon body. The silicon body is surrounded by a gate material on three sides. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The MBT-FET combines the advantages of a wide fin device and a narrow fin device.

    摘要翻译： 多体厚度（MBT）场效应晶体管（FET）包括形成在衬底上的硅体。 硅体可以包括在宽部分和基底之间的宽的部分和窄的部分。 硅体可以包括多于一对宽的部分和窄的部分，每对位于硅体的不同高度处。 硅体由三面的栅极材料包围。 衬底可以是体硅衬底或绝缘体上硅（SOI）衬底。 MBT-FET结合了宽鳍片器件和窄鳍片器件的优点。

    Methods for uniform doping of non-planar transistor structures
    43.
    发明申请
    Methods for uniform doping of non-planar transistor structures 有权
    均匀掺杂非平面晶体管结构的方法

    公开(公告)号：US20080085580A1

    公开(公告)日：2008-04-10

    申请号：US11529963

    申请日：2006-09-29

    申请人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    发明人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    IPC分类号： H01L21/8238 ,  H01L29/94

    CPC分类号： H01L21/823437 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

    摘要： Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.

    摘要翻译： 用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。 可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。 可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。 可以去除掩模，从而产生均匀掺杂的硅体。

    Methods for uniform doping of non-planar transistor structures
    49.
    发明授权
    Methods for uniform doping of non-planar transistor structures 有权
    均匀掺杂非平面晶体管结构的方法

    公开(公告)号：US07494862B2

    公开(公告)日：2009-02-24

    申请号：US11529963

    申请日：2006-09-29

    申请人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    发明人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823437 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

    摘要： Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.

    摘要翻译： 用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。 可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。 可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。 可以去除掩模，从而产生均匀掺杂的硅体。