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151 条记录 (耗时 0.051 秒)

    Multi-electron beam source with driving circuit for preventing voltage spikes
    42.
    发明授权
    Multi-electron beam source with driving circuit for preventing voltage spikes 失效
    具有用于防止电压尖峰的驱动电路的多电子束源

    公开(公告)号：US6157137A

    公开(公告)日：2000-12-05

    申请号：US956170

    申请日：1997-10-22

    申请人： Hidetoshi Suzuki ,  Ichiro Nomura ,  Tetsuya Kaneko ,  Haruhito Ono

    发明人： Hidetoshi Suzuki ,  Ichiro Nomura ,  Tetsuya Kaneko ,  Haruhito Ono

    IPC分类号： G09G3/22 ,  G09G3/10

    CPC分类号： G09G3/22 ,  G09G2320/043 ,  H01J2201/3165 ,  H01J2329/00

    摘要： A multi-electron beam source comprises an electron emitting element part including: a plurality of electron emitting elements provided two-dimensionally in a matrix-like arrangement on a substrate; opposing terminals of electron emitting elements arranged adjacently in the column direction thereof being electrically connected to each other; terminals on the same side of all the electron emitting elements in the same row being electrically connected; and the plurality of electron emitting elements being arranged in "m" rows, "m" representing a number of two or more, and a driving circuit part for driving said electron emitting element part. The multi-electron beam source has means for removing a spike noise superposed onto the driving pulse generated by said driving cirucit part.

    摘要翻译： 多电子束源包括电子发射元件部分，包括：在基板上以矩阵状布置二维地设置的多个电子发射元件; 电子发射元件在其列方向上相邻布置的相对端子彼此电连接; 同一行中所有电子发射元件的同一侧的端子电连接; 并且多个电子发射元件以“m”行排列，“m”表示两个或更多个数量，以及用于驱动所述电子发射元件部分的驱动电路部分。 多电子束源具有用于去除叠加在由所述驱动尖锐部分产生的驱动脉冲上的尖峰噪声的装置。

    Semiconductor memory device
    46.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5740113A

    公开(公告)日：1998-04-14

    申请号：US571135

    申请日：1995-12-12

    申请人： Tetsuya Kaneko

    发明人： Tetsuya Kaneko

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00

    CPC分类号： G11C11/4087 ,  G11C11/4085 ,  G11C11/4091 ,  G11C5/145

    摘要： A semiconductor device constituted by a booster circuit, memory cell arrays, a sense amplifier circuit, transmission gate circuits, equalizing circuits and a control circuit applying a boosted potential respectively to the gates of MOS transistors of the transmission gate circuits and the equalizing circuits when no memory cells of the memory cell arrays are selected whereby the capacitance of de-coupling capacitors connected to output terminals of the booster circuit can be reduced thereby contributing to reduction in chip area.

    摘要翻译： 由升压电路，存储单元阵列，读出放大器电路，传输门电路，均衡电路和控制电路构成的半导体器件，分别向传输门电路和均衡电路的MOS晶体管的栅极施加升压电位，当没有 选择存储单元阵列的存储单元，由此可以减小连接到升压电路的输出端的去耦电容器的电容，从而有助于减少芯片面积。

    Semiconductor memory device having voltage booster circuit coupled to a bit line charging/equalizing circuit or switch
    47.
    发明授权
    Semiconductor memory device having voltage booster circuit coupled to a bit line charging/equalizing circuit or switch 失效
    具有耦合到位线充电/均衡电路或开关的升压电路的半导体存储器件

    公开(公告)号：US5689461A

    公开(公告)日：1997-11-18

    申请号：US469696

    申请日：1995-06-06

    申请人： Tetsuya Kaneko ,  Takashi Ohsawa

    发明人： Tetsuya Kaneko ,  Takashi Ohsawa

    IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C8/08 ,  G11C11/4094 ,  G11C5/145 ,  G11C5/147 ,  G11C7/12

    摘要： An equalizing circuit is connected between a pair of bit lines. The equalizing circuit is made up of three MOS transistors and an equalization control signal is supplied to the gates of the MOS transistors. A sense amplifier circuit is connected to the bit lines. The sense amplifier circuit amplifies the potential difference occurring between the bit lines, for the detection of data. The equalization control signal is output from a level conversion circuit. An internal boosted voltage-generating circuit constantly generates a boosted voltage which is higher than an externally-applied power supply voltage applied to a power supply terminal. The boosted voltage is applied to the level conversion circuit. The level conversion circuit converts an input control signal, whose high-level voltage is equal to, or lower than the externally-applied power supply voltage, into the boosted voltage, thereby generating the equalization control signal.

    摘要翻译： 均衡电路连接在一对位线之间。 均衡电路由三个MOS晶体管组成，并且均衡控制信号被提供给MOS晶体管的栅极。 读出放大器电路连接到位线。 读出放大器电路放大位线之间出现的电位差，用于检测数据。 均衡控制信号从电平转换电路输出。 内部升压产生电路不断地产生比施加到电源端子的外部施加的电源电压高的升压电压。 升压电压被施加到电平转换电路。 电平转换电路将其高电平等于或低于外部施加电源电压的输入控制信号转换为升压电压，从而产生均衡控制信号。

    Liquid crystal display device with pixels having stripe-shaped projections with equal heights
    49.
    发明授权
    Liquid crystal display device with pixels having stripe-shaped projections with equal heights 失效
    具有像素的液晶显示装置具有相同高度的条状突起

    公开(公告)号：US5604613A

    公开(公告)日：1997-02-18

    申请号：US452019

    申请日：1995-05-26

    申请人： Katsuhiko Shinjo ,  Tetsuya Kaneko ,  Shuzo Kaneko ,  Takeo Tsukamoto

    发明人： Katsuhiko Shinjo ,  Tetsuya Kaneko ,  Shuzo Kaneko ,  Takeo Tsukamoto

    IPC分类号： G02F1/1333 ,  G02F1/1343 ,  G02F1/141 ,  G02F1/13

    CPC分类号： G02F1/133371 ,  G02F1/133345 ,  G02F1/141 ,  G02F1/13439

    摘要： A liquid crystal display device is constituted by a pair of oppositely disposed substrates each having a plurality of opposing electrodes, and a ferroelectric liquid crystal disposed between the substrates so as to form a plurality of pixels each composed by a combination of a pair of the opposing electrodes and the ferroelectric liquid crystal disposed therebetween. Each pixel is provided with regions of different polarity inversion threshold voltages, and at least one of the pair of opposing electrodes is provided with a plurality of regions having unevennesses at different densities including a region with a higher density of unevennesses corresponding to a region of a lower polarity inversion threshold voltage and a region with a lower density of unevennesses corresponding to a region of a higher polarity inversion threshold voltage.

    摘要翻译： 液晶显示装置由一对相对设置的基板构成，每个基板具有多个相对的电极，并且设置在基板之间的铁电液晶以形成多个像素，每个像素由一对相对的电极组合 电极和设置在其间的铁电液晶。 每个像素设置有不同极性的反转阈值电压的区域，并且该对相对电极中的至少一个设置有多个具有不同密度的不均匀区域，该区域具有对应于 低极性反转阈值电压和对应于较高极性反转阈值电压的区域的具有较低密度的不均匀区域。