公开(公告)号：US20230163869A1

公开(公告)日：2023-05-25

申请号：US17534776

申请日：2021-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen ,  Liron Mula

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.

公开(公告)号：US11637557B2

公开(公告)日：2023-04-25

申请号：US17670540

申请日：2022-02-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ran Ravid ,  Aviv Berg ,  Lavi Koch ,  Chen Gaist ,  Dotan David Levi

IPC: H03L7/08 ,  G06F1/12 ,  H04L7/033 ,  H03L7/099

Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

公开(公告)号：US20220416925A1

公开(公告)日：2022-12-29

申请号：US17359667

申请日：2021-06-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

IPC: H04J3/06

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

公开(公告)号：US20220385598A1

公开(公告)日：2022-12-01

申请号：US17824954

申请日：2022-05-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Boris Pismenny ,  Dotan David Levi ,  Gal Yefet

IPC: H04L49/552 ,  H04L49/90 ,  H04L49/9057 ,  H04W28/04 ,  H04L49/901 ,  H04L65/61 ,  H04L65/65

Abstract: A method for communication includes mapping transport sequence numbers in headers of data packets received from a network to respective buffers in a memory of a host computer. At least a part of the data from payloads of the received data packets is written directly to the respective buffers.

公开(公告)号：US11476928B2

公开(公告)日：2022-10-18

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04L49/351 ,  H04L49/90 ,  H04W72/04 ,  H04W74/08

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US20220283964A1

公开(公告)日：2022-09-08

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/1045 ,  G06F15/173 ,  G06F9/46 ,  G06F9/455

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US11388263B2

公开(公告)日：2022-07-12

申请号：US17067690

申请日：2020-10-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Lior Narkis ,  Avi Urman

IPC: H04L49/90 ,  H04L67/5681 ,  H04W72/12

Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.

公开(公告)号：US20220209943A1

公开(公告)日：2022-06-30

申请号：US17227321

申请日：2021-04-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dimitrios Syrivelis ,  Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Elad Mentovich ,  Dotan David Levi

IPC: H04L9/08 ,  H04L29/06 ,  G06F12/14 ,  G06N10/00

Abstract: In one embodiment, a secure computing system comprises a key generation sub-system configured to generate cryptographic keys and corresponding key labels for distribution to computer dusters, each computer cluster including a plurality of respective endpoints, a plurality of quantum key distribution (QKD) devices connected via respective optical fiber connections, and configured to securely distribute the generated cryptographic keys among the computer clusters, and a key orchestration sub-system configured to manage caching of the cryptographic keys in advance of receiving key requests from applications running on ones of the endpoints, and provide respective ones of the cryptographic keys to the applications to enable secure communication among the applications.

公开(公告)号：US20220191275A1

公开(公告)日：2022-06-16

申请号：US17120313

申请日：2020-12-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avraham Ganor ,  Arnon Sattinger ,  Natan Manevich ,  Reuven Kogan ,  Artiom Tsur ,  Ariel Almog ,  Bar Shapira

IPC: H04L29/08 ,  G06F1/12 ,  G06F1/14

Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

公开(公告)号：US20220116473A1

公开(公告)日：2022-04-14

申请号：US17067690

申请日：2020-10-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Lior Narkis ,  Avi Urman

IPC: H04L29/08

Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.