公开(公告)号：US09136278B2

公开(公告)日：2015-09-15

申请号：US14083056

申请日：2013-11-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

IPC: H01L27/115 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3205 ,  H01L27/108

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4966

Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

Abstract translation: 一些实施例包括制造集成结构的方法。 在交替的第一和第二水平的叠层上形成含金属的材料。 通过含金属材料和叠层形成开口。 在开口的侧壁处沿着堆叠形成重叠的垂直堆叠的电部件。 一些实施例包括形成垂直堆叠的存储单元的方法。 含金属的材料形成在交替的二氧化硅水平和导电掺杂的硅层上。 通过含金属材料和叠层形成第一开口。 腔体形成为延伸到沿着第一开口的侧壁的导电掺杂的硅层中。 电荷阻挡电介质和电荷存储结构形成在空腔内以留下第二开口。 第二开口的侧壁衬有栅极电介质，然后在第二开口内形成通道材料。

公开(公告)号：US09041090B2

公开(公告)日：2015-05-26

申请号：US13894631

申请日：2013-05-15

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Akira Goda ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/115 ,  H01L27/105 ,  H01L29/792 ,  H01L29/788 ,  H01L29/76 ,  H01L21/8239 ,  H01L21/336 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L27/1052 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.

Abstract translation: 公开了形成一串存储单元的方法和具有垂直的存储单元串的装置。 一个这样的存储单元串可以至少部分地形成为包括多个交替级控制栅极材料和绝缘体材料的堆叠材料。 串的存储单元可以包括与控制栅极材料的电平的控制栅极材料的级别相邻的浮动栅极材料。 存储单元还可以包括与浮栅材料相邻的隧道介电材料。 控制栅极材料和隧道电介质材料的水平面与浮栅材料的相邻表面相邻。 存储单元可以沿着隧道介电材料和浮栅材料之间的界面包括金属。 存储单元还可以包括与隧道电介质材料相邻的半导体材料。

公开(公告)号：US20150140753A1

公开(公告)日：2015-05-21

申请号：US14083056

申请日：2013-11-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4966

Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

公开(公告)号：US20150123189A1

公开(公告)日：2015-05-07

申请号：US14069574

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

公开(公告)号：US20140339621A1

公开(公告)日：2014-11-20

申请号：US13894631

申请日：2013-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fatma Arzum Simsek-Ege ,  Akira Goda ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/1052 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.

Abstract translation: 公开了形成一串存储单元的方法和具有垂直的存储单元串的装置。 一个这样的存储单元串可以至少部分地形成为包括多个交替级控制栅极材料和绝缘体材料的堆叠材料。 串的存储单元可以包括与控制栅极材料的电平的控制栅极材料的级别相邻的浮动栅极材料。 存储单元还可以包括与浮栅材料相邻的隧道介电材料。 控制栅极材料和隧道电介质材料的水平面与浮栅材料的相邻表面相邻。 存储单元可以沿着隧道介电材料和浮栅材料之间的界面包括金属。 存储单元还可以包括与隧道电介质材料相邻的半导体材料。

公开(公告)号：US20250078911A1

公开(公告)日：2025-03-06

申请号：US18745943

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Haitao Liu ,  David A. Daycock

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4091 ,  H10B12/00

Abstract: A microelectronic device includes memory cells, hieratical digit line (HDL) structures, and sense amplifier (SA) devices. The memory cells are within an array region and respectively include an access device and a storage node device vertically underlying and coupled to the access device. The HDL structures are within the array region and vertically overlie and are coupled to the memory cells. The HDL structures respectively include a lower section, an upper section vertically overlying and at least partially horizontally offset from the lower section, and a middle section vertically extending from and between the lower section and the upper section. The SA devices are within the array region and vertically overlie and are coupled to the HDL structures. Related methods, memory devices, and electronic systems are also described.

公开(公告)号：US12243580B2

公开(公告)日：2025-03-04

申请号：US17936760

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

IPC: G11C11/00 ,  G11C11/4091 ,  H01L25/065 ,  H01L25/18

Abstract: Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.

公开(公告)号：US20250063719A1

公开(公告)日：2025-02-20

申请号：US18935380

申请日：2024-11-01

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H10B12/00 ,  G11C5/02 ,  G11C5/10 ,  G11C11/407

Abstract: A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20250006249A1

公开(公告)日：2025-01-02

申请号：US18765076

申请日：2024-07-05

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  H10B80/00

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US12137549B2

公开(公告)日：2024-11-05

申请号：US17461095

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H10B12/00 ,  G11C5/02 ,  G11C5/10 ,  G11C11/407

Abstract: A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.