中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.035 seconds)

    BANK CONFIGURABLE POWER MODES
    41.
    发明申请
    BANK CONFIGURABLE POWER MODES 有权

    公开(公告)号：US20210064119A1

    公开(公告)日：2021-03-04

    申请号：US16551581

    申请日：2019-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent

    IPC: G06F1/3287 ,  G06F1/3234 ,  G06F1/28 ,  G11C11/22 ,  G11C11/4096

    Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

    ACCESS SCHEMES FOR ACTIVITY-BASED DATA PROTECTION IN A MEMORY DEVICE
    42.
    发明申请
    ACCESS SCHEMES FOR ACTIVITY-BASED DATA PROTECTION IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20200058341A1

    公开(公告)日：2020-02-20

    申请号：US16104693

    申请日：2018-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Corrado Villa ,  Andrea Martinelli

    IPC: G11C11/22 ,  G06F3/06

    Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

    Shared decoder architecture for three-dimensional memory arrays
    44.
    发明授权
    Shared decoder architecture for three-dimensional memory arrays 有权

    公开(公告)号：US12260907B2

    公开(公告)日：2025-03-25

    申请号：US18622033

    申请日：2024-03-29

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

    IPC: G11C13/04 ,  G11C13/00

    Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

    Decoding architecture for memory tiles
    47.
    发明授权
    Decoding architecture for memory tiles 有权

    公开(公告)号：US11804264B2

    公开(公告)日：2023-10-31

    申请号：US17943591

    申请日：2022-09-13

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

    IPC: G11C16/04 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

    CPC classification number: G11C13/0028 ,  G11C13/0004 ,  G11C13/004 ,  H10B63/34 ,  H10B63/845 ,  H10N70/231 ,  G11C2213/75

    Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

    Access schemes for activity-based data protection in a memory device
    48.
    发明授权
    Access schemes for activity-based data protection in a memory device 有权

    公开(公告)号：US11651809B2

    公开(公告)日：2023-05-16

    申请号：US17231704

    申请日：2021-04-15

    Applicant: Micron Technology, inc.

    Inventor： Corrado Villa ,  Andrea Martinelli

    IPC: G06F3/06 ,  G11C11/22

    CPC classification number: G11C11/2259 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2295

    Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

    Decoding architecture for memory tiles
    49.
    发明授权
    Decoding architecture for memory tiles 有权

    公开(公告)号：US11475947B1

    公开(公告)日：2022-10-18

    申请号：US17231668

    申请日：2021-04-15

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Andrea Martinelli ,  Claudio Nava

    IPC: G11C16/04 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

    BALANCING DATA FOR STORAGE IN A MEMORY DEVICE
    50.
    发明申请
    BALANCING DATA FOR STORAGE IN A MEMORY DEVICE 有权

    公开(公告)号：US20220253237A1

    公开(公告)日：2022-08-11

    申请号：US17677586

    申请日：2022-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

    IPC: G06F3/06

    Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

Patent Agency Ranking