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    MEMORY APPARATUS AND SYSTEM WITH SHARED WORDLINE DECODER
    2.
    发明申请
    MEMORY APPARATUS AND SYSTEM WITH SHARED WORDLINE DECODER 有权
    具有共享字词解码器的存储器和系统

    公开(公告)号：US20140233338A1

    公开(公告)日：2014-08-21

    申请号：US14261674

    申请日：2014-04-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

    IPC: G11C8/10

    CPC classification number: G11C8/10 ,  G11C5/025 ,  G11C8/14

    Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

    Abstract translation: 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。

    APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES
    4.
    发明申请
    APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES 有权
    提供存储器件电源管理的装置和方法

    公开(公告)号：US20150235676A1

    公开(公告)日：2015-08-20

    申请号：US14703668

    申请日：2015-05-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Gerald Barkley ,  Nicholas Hendrickson

    IPC: G11C5/14

    CPC classification number: G11C5/147 ,  G11C5/14 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/3427

    Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

    Abstract translation: 在一些实施方式中，诸如非易失性固态存储器件的装置可以包括存取线偏置电路，以响应于模式信息来设置与存储器芯的取消选择的存取线相关联的偏置电平。 在一种方法中，接入线偏置电路可以使用线性下调来改变存储器核心的取消选择的接入线路上的电压电平。 可以提供诸如主机处理器的存储器访问设备，其能够动态地设置存储器设备的存储器核心的操作模式，以便管理存储器的功耗。 还提供了其他装置和方法。

    Apparatus and methods to provide power management for memory devices
    6.
    发明授权
    Apparatus and methods to provide power management for memory devices 有权
    为存储器件提供电源管理的装置和方法

    公开(公告)号：US09025407B2

    公开(公告)日：2015-05-05

    申请号：US14457039

    申请日：2014-08-11

    Applicant: Micron Technology, Inc.

    Inventor： Gerald Barkley ,  Nicholas Hendrickson

    IPC: G11C5/14

    CPC classification number: G11C5/147 ,  G11C5/14 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/3427

    Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

    Abstract translation: 在一些实施方式中，诸如非易失性固态存储器件的装置可以包括存取线偏置电路，以响应于模式信息来设置与存储器芯的取消选择的存取线相关联的偏置电平。 在一种方法中，接入线偏置电路可以使用线性下调来改变存储器核心的取消选择的接入线路上的电压电平。 可以提供诸如主机处理器的存储器访问设备，其能够动态地设置存储器设备的存储器核心的操作模式，以便管理存储器的功耗。 还提供了其他装置和方法。

    Memory apparatus and system with shared wordline decoder
    7.
    发明授权
    Memory apparatus and system with shared wordline decoder 有权
    具有共享字线解码器的存储器和系统

    公开(公告)号：US09406363B2

    公开(公告)日：2016-08-02

    申请号：US14261674

    申请日：2014-04-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

    IPC: G11C8/00 ,  G11C8/10 ,  G11C5/02 ,  G11C8/14

    CPC classification number: G11C8/10 ,  G11C5/025 ,  G11C8/14

    Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

    Abstract translation: 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。

    Staggered programming for resistive memories
    8.
    发明授权
    Staggered programming for resistive memories 有权
    电阻存储器的交错编程

    公开(公告)号：US09164894B2

    公开(公告)日：2015-10-20

    申请号：US14165265

    申请日：2014-01-27

    Applicant: Micron Technology Inc.

    Inventor： Gerald Barkley ,  Sunil Shetty ,  Andrea Martinelli

    IPC: G06F12/00 ,  G06F12/02 ,  G11C13/00

    CPC classification number: G06F12/0246 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0088

    Abstract: Subject matter disclosed herein relates to a memory device and method of programming same. In some embodiments, a memory device can be programmed by partitioning information into a plurality of chunks. Partitioning can be performed by determining a pattern of logic ones and zeroes, and setting a size of an information chunk based on the pattern of logic ones and zeroes.

    Abstract translation: 本文公开的主题涉及一种对其进行编程的存储器件及其方法。 在一些实施例中，可以通过将信息划分成多个块来编程存储器设备。 可以通过确定逻辑1和零的模式来执行分区，并且基于逻辑1和零的模式来设置信息块的大小。

    APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES
    9.
    发明申请
    APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES 有权
    提供存储器件电源管理的装置和方法

    公开(公告)号：US20140347947A1

    公开(公告)日：2014-11-27

    申请号：US14457039

    申请日：2014-08-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Gerald Barkley ,  Nicholas Hendrickson

    IPC: G11C5/14

    CPC classification number: G11C5/147 ,  G11C5/14 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/3427

    Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

    Abstract translation: 在一些实施方式中，诸如非易失性固态存储器件的装置可以包括存取线偏置电路，以响应于模式信息来设置与存储器芯的取消选择的存取线相关联的偏置电平。 在一种方法中，接入线偏置电路可以使用线性下调来改变存储器核心的取消选择的接入线路上的电压电平。 可以提供诸如主机处理器的存储器访问设备，其能够动态地设置存储器设备的存储器核心的操作模式，以便管理存储器的功耗。 还提供了其他装置和方法。

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