公开(公告)号：US20240222184A1

公开(公告)日：2024-07-04

申请号：US18508239

申请日：2023-11-14

Applicant: Micron Technology, Inc.

Inventor： Jeremy E. Minnich ,  Andrew M. Bayless

IPC: H01L21/683 ,  H01L21/306 ,  H01L21/782 ,  H01L25/065

CPC classification number: H01L21/6836 ,  H01L21/30625 ,  H01L21/782 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586

Abstract: A semiconductor substrate is provided. The semiconductor substrate includes a center portion and a peripheral portion. The semiconductor substrate further includes an annulus of sacrificial material disposed at a front side of the semiconductor substrate and extending at least partially through the semiconductor substrate. The annulus of sacrificial material separates the center portion of the substrate from the peripheral portion of the substrate at the front side. The semiconductor substrate can be thinned to expose the annulus of sacrificial material and disconnect the peripheral portion from the center portion. In doing so, the thinned substrate may have a planar substrate edge void of sharp edges, thereby increasing its mechanical robustness.

公开(公告)号：US20240038707A1

公开(公告)日：2024-02-01

申请号：US17875778

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Cassie M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/13019 ,  H01L2224/13582 ,  H01L2224/81815 ,  H01L2224/13147 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13124 ,  H01L2224/13184 ,  H01L2224/13157 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/1369 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13613 ,  H01L2224/13609 ,  H01L2224/13618 ,  H01L2224/1362

Abstract: In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

公开(公告)号：US20240006223A1

公开(公告)日：2024-01-04

申请号：US18368449

申请日：2023-09-14

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/6836 ,  H01L21/4814 ,  H01L23/481

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

公开(公告)号：US11784050B2

公开(公告)日：2023-10-10

申请号：US17241386

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L21/76859 ,  H01L21/78 ,  H01L21/26513

Abstract: A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.

公开(公告)号：US11764096B2

公开(公告)日：2023-09-19

申请号：US16923754

申请日：2020-07-08

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/6836 ,  H01L21/4814 ,  H01L23/481

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

公开(公告)号：US20230268334A1

公开(公告)日：2023-08-24

申请号：US18310481

申请日：2023-05-01

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Bradley R. Bitz

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/70 ,  H01L21/82

CPC classification number: H01L25/50 ,  H01L21/70 ,  H01L21/78 ,  H01L21/82 ,  H01L24/29 ,  H01L25/0652

Abstract: A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.

公开(公告)号：US20210183806A1

公开(公告)日：2021-06-17

申请号：US16715594

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/29

Abstract: Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components, and related material films, articles and assemblies.

公开(公告)号：US20210183702A1

公开(公告)日：2021-06-17

申请号：US16713309

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/50

Abstract: Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.

公开(公告)号：US10770422B2

公开(公告)日：2020-09-08

申请号：US16236449

申请日：2018-12-29

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Cassie L. Bayless

IPC: H01L23/00 ,  H01L21/66 ,  B32B37/12

Abstract: A bond chuck having individually-controllable regions, and associated systems and methods are disclosed herein. The bond chuck comprises a plurality of individual regions that are movable relative to one another in a longitudinal direction. In some embodiments, the individual regions include a first region having a first outer surface, and a second region peripheral to the first region and including a second outer surface. The first region is movable in a longitudinal direction to a first position, and the second region is movable in the longitudinal direction to a second position, such that in the second position, the second outer surface of the second region extends longitudinally beyond the first outer surface of the first region. The bond chuck can be positioned proximate a substrate of a semiconductor device such that movement of the first region and/or second region affect a shape of the substrate, which thereby causes an adhesive on the substrate to flow in a lateral, predetermined direction.

公开(公告)号：US10763186B2

公开(公告)日：2020-09-01

申请号：US16237111

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Wayne H. Huang ,  Owen R. Fay

IPC: H01L23/31 ,  H01L23/473 ,  H01L21/56 ,  H01L23/36 ,  H01L23/467

Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.