公开(公告)号：US20240038707A1

公开(公告)日：2024-02-01

申请号：US17875778

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Cassie M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/13019 ,  H01L2224/13582 ,  H01L2224/81815 ,  H01L2224/13147 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13124 ,  H01L2224/13184 ,  H01L2224/13157 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/1369 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13613 ,  H01L2224/13609 ,  H01L2224/13618 ,  H01L2224/1362

Abstract: In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

公开(公告)号：US09754907B2

公开(公告)日：2017-09-05

申请号：US15133514

申请日：2016-04-20

Applicant: Cufer Asset Ltd. L.L.C.

Inventor： Roger Dugas ,  John Trezza

IPC: B44C1/165 ,  B29C65/00 ,  H01L23/427 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/556 ,  H01L25/065 ,  H01L25/18 ,  H01S5/042 ,  H01S5/183 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00 ,  H01L23/488 ,  H01S5/022

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/24226 ,  H01L2224/45111 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81825 ,  H01L2224/81894 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/18308 ,  H01S2301/176 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

公开(公告)号：US09620468B2

公开(公告)日：2017-04-11

申请号：US14074637

申请日：2013-11-07

Applicant: TONGFU MICROELECTRONICS CO., LTD.

Inventor： Chang-Ming Lin ,  Yu-Juan Tao

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/81191 ,  H01L2924/12042 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/00

Abstract: Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.

公开(公告)号：US20160336286A1

公开(公告)日：2016-11-17

申请号：US15221370

申请日：2016-07-27

Applicant: Invensas Corporation

Inventor： Rajesh KATKAR ,  Cyprian Emeka UZOH

IPC: H01L23/00 ,  H05K3/34 ,  H05K1/14 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L24/14 ,  B23K1/0016 ,  B23K3/0623 ,  B23K35/0244 ,  B23K35/0266 ,  B23K2101/40 ,  H01L21/02225 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0391 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/06102 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11318 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1405 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75253 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8122 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/115 ,  H05K1/144 ,  H05K3/341 ,  H05K2201/09572 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2224/81 ,  H01L2224/83

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

公开(公告)号：US20160240509A1

公开(公告)日：2016-08-18

申请号：US15135364

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungkyu KWON ,  Kang Joon LEE ,  JaeWook YOO ,  Su-Chang LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract translation: 半导体封装包括包括中心部分和周边部分的第一基板，附接到第一基板的中心部分的至少一个第一中心连接部件和附接到第一基板的周边部分的至少一个第一周边连接部件。 第一中心连接构件包括第一支撑件和围绕第一支撑件的第一融合导电层。

公开(公告)号：US09379084B2

公开(公告)日：2016-06-28

申请号：US14682914

申请日：2015-04-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L33/62

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

公开(公告)号：US09324629B2

公开(公告)日：2016-04-26

申请号：US11693984

申请日：2007-03-30

Applicant: Roger Dugas ,  John Trezza

Inventor： Roger Dugas ,  John Trezza

IPC: B44C1/165 ,  B29C65/00 ,  H01L23/427 ,  H01L21/48 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01S5/042 ,  H01L23/488 ,  H01S5/022 ,  H01S5/183

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/24226 ,  H01L2224/45111 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81825 ,  H01L2224/81894 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/18308 ,  H01S2301/176 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

Abstract translation: 一种使用多个芯片的方法，每个芯片分别具有包括电触点的接合表面和与接合表面相对的一侧的表面，包括使位于主体上的可硬化材料与多个芯片接触，硬化可硬化材料，从而 约束多个芯片中的每一个的至少一部分，将多个芯片从第一位置移动到第二位置，向身体施加力，使得硬化的可硬化材料将均匀地传递施加到身体的垂直力， 以在每个单独的芯片的接合表面与第二位置处的单个芯片将被接合的元件的接合表面接触的同时，不会对各个芯片元件造成损害， ，或粘结面。

公开(公告)号：US09269683B2

公开(公告)日：2016-02-23

申请号：US14200613

申请日：2014-03-07

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/12 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract translation: 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US20160035707A1

公开(公告)日：2016-02-04

申请号：US14883135

申请日：2015-10-14

Applicant: WIN Semiconductors Corp.

Inventor： Chang-Hwang HUA ,  Chih-Hsien LIN

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L23/31 ,  H01L23/29 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/06 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0105 ,  H01L2924/014

Abstract: A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.

Abstract translation: 层叠结构包括半导体芯片，其包括具有穿透基板的至少一个基板通孔的基板; 至少一个背面金属层，其形成在所述基板的背面上，覆盖所述基板通孔的内表面和所述基板的背面的至少一部分; 至少一个前侧金属层，形成在所述基板的前侧，并且在所述至少一个基板通孔中的至少一个的顶部上电连接到所述至少一个背侧金属层; 至少一个电子器件，其形成在所述衬底的前侧上并电连接到所述至少一个前侧金属层; 以及形成在背侧金属层和前侧金属层中的至少一个上的至少一个金属凸块。

公开(公告)号：US09219045B2

公开(公告)日：2015-12-22

申请号：US14160796

申请日：2014-01-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有轨迹线和集成凸块焊盘的衬底。 导电凸块材料沉积在衬底凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得凸块材料设置在管芯凸块焊盘和衬底凸块焊盘之间。 凸块材料在芯片凸块焊盘或基板凸块焊盘周围没有焊接掩模回流以形成互连。 凸块材料在管芯凸块焊盘或衬底凸块焊盘的占用面积内自我限制。 在回流之前，凸起材料可以浸入助熔剂溶液中以增加润湿性。 或者，互连包括不可熔基底和可熔盖。 选择凸起材料的体积，使得表面张力在回流期间保持凸块内的凸起材料的自我约束。