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    Apparatuses and methods of reading memory cells based on response to a test pulse
    42.
    发明授权
    Apparatuses and methods of reading memory cells based on response to a test pulse 有权

    公开(公告)号：US09672908B2

    公开(公告)日：2017-06-06

    申请号：US14977411

    申请日：2015-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C7/00 ,  G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0057

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    43.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 有权
    跨点存储器及其制造方法

    公开(公告)号：US20160056208A1

    公开(公告)日：2016-02-25

    申请号：US14468036

    申请日：2014-08-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Andrea Ghetti

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

    Abstract translation: 所公开的技术通常涉及集成电路器件，特别涉及交叉点存储器阵列及其制造方法。 形成线堆叠，包括设置在导线下方的存储材料线。 上导电线形成在线堆叠上并与线堆叠交叉，使相邻的上导线之间的线堆叠的部分暴露。 在形成上导线之后，通过从线堆叠的暴露部分去除存储材料，使得每个存储元件被空间横向包围，在下导电线和上导线之间的交叉处形成存储元件。 连续的密封材料横向围绕每个存储元件。

    APPARATUSES AND METHODS OF READING MEMORY CELLS
    44.
    发明申请
    APPARATUSES AND METHODS OF READING MEMORY CELLS 有权
    读取记忆细胞的装置和方法

    公开(公告)号：US20150294716A1

    公开(公告)日：2015-10-15

    申请号：US14251002

    申请日：2014-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0057

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

    Abstract translation: 所公开的技术通常涉及其操作的存储装置和方法，更具体地涉及读取存储器阵列（诸如交叉点存储器阵列）中的存储器单元的存储器阵列和方法。 在一个方面，所述方法包括提供包括以多种状态之一的存储器单元的存储器阵列。 该方法还包括确定存储器单元的阈值电压（Vth）是否具有在预定读取电压窗口内的值。 如果确定阈值电压具有预定读取电压窗口内的值，则将测试脉冲施加到存储器单元。 可以基于存储器单元对测试脉冲的响应来确定存储器单元的状态，其中该状态在接收测试脉冲之前对应于存储单元的多个状态中的一个状态。

    PULSE BASED MULTI-LEVEL CELL PROGRAMMING
    47.
    发明公开
    PULSE BASED MULTI-LEVEL CELL PROGRAMMING 审中-公开

    公开(公告)号：US20240347081A1

    公开(公告)日：2024-10-17

    申请号：US18633362

    申请日：2024-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C7/10 ,  G11C16/34

    CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/3404

    Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.

    MEMORY DEVICE AND METHOD FOR OPERATING THE SAME
    48.
    发明公开
    MEMORY DEVICE AND METHOD FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20240194258A1

    公开(公告)日：2024-06-13

    申请号：US18586174

    申请日：2024-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli

    IPC: G11C13/00 ,  G11C29/02 ,  G11C29/12

    CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/12005

    Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

    Memory device and method for operating the same
    49.
    发明授权
    Memory device and method for operating the same 有权

    公开(公告)号：US11915750B2

    公开(公告)日：2024-02-27

    申请号：US17862391

    申请日：2022-07-11

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli

    IPC: G11C13/00 ,  G11C29/02 ,  G11C29/12

    CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/12005

    Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

    Cross-point pillar architecture for memory arrays
    50.
    发明授权
    Cross-point pillar architecture for memory arrays 有权

    公开(公告)号：US11887661B2

    公开(公告)日：2024-01-30

    申请号：US17647578

    申请日：2022-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

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