公开(公告)号：US08609324B2

公开(公告)日：2013-12-17

申请号：US13852275

申请日：2013-03-28

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran

IPC: G03F7/20

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/11521

Abstract: Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.

公开(公告)号：US20130320552A1

公开(公告)日：2013-12-05

申请号：US13962208

申请日：2013-08-08

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

IPC: H01L23/544

CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

公开(公告)号：US20220278120A1

公开(公告)日：2022-09-01

申请号：US17746649

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

IPC: H01L27/11556 ,  H01L27/1157 ,  G11C5/06 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11582

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

公开(公告)号：US20220262626A1

公开(公告)日：2022-08-18

申请号：US17662160

申请日：2022-05-05

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Raghupathy Giridhar

IPC: H01L21/027 ,  H01L21/033 ,  H01L27/105 ,  H01L21/3213 ,  H01L21/311

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

公开(公告)号：US11195854B2

公开(公告)日：2021-12-07

申请号：US16783981

申请日：2020-02-06

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20190148135A1

公开(公告)日：2019-05-16

申请号：US16249369

申请日：2019-01-16

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Raghupathy Giridhar

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/033 ,  H01L27/105 ,  H01L21/3213

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

公开(公告)号：US20180358378A1

公开(公告)日：2018-12-13

申请号：US16107294

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H05K999/99

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20180204851A1

公开(公告)日：2018-07-19

申请号：US15924143

申请日：2018-03-16

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/11582 ,  H01L29/49 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US20170365617A1

公开(公告)日：2017-12-21

申请号：US15679727

申请日：2017-08-17

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20160233225A1

公开(公告)日：2016-08-11

申请号：US14619243

申请日：2015-02-11

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

Abstract translation: 一些实施例包括沿着半导体材料的垂直沟道形成的一串电荷存储装置; 漏极选择栅极（SGD）晶体管的栅极区域，所述栅极区域至少部分地围绕所述垂直沟道; 在所述栅极区域中形成的介质阻挡层; 形成在所述栅极区域和所述电介质屏障之上的第一隔离层; 形成在垂直沟道上方的SGD晶体管的漏极区域; 以及形成在所述第一隔离层和所述漏极区之上的第二隔离层，其中所述第二隔离层包括与所述SGD晶体管的漏极区域电接触的导电接触。 公开了附加的装置和方法。