公开(公告)号：US11676917B2

公开(公告)日：2023-06-13

申请号：US17103447

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L23/60 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11529

CPC classification number: H01L23/60 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

公开(公告)号：US11563117B1

公开(公告)日：2023-01-24

申请号：US17487058

申请日：2021-09-28

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/40 ,  H01L21/266 ,  H01L29/66 ,  H01L27/088

Abstract: An apparatus includes a substrate and a transistor disposed on the substrate. The transistor includes a source and a source contact disposed on the source. The transistor also includes a drain and a drain contact disposed on the drain. A gate is disposed between the source contact and the drain contact, and a screened region is disposed adjacent the source contact or the drain contact. The screened region corresponds to a lightly doped region. The screened region includes an implant screen configured to reduce an effective dose in the screened region so as to shift an acceptable dose range of the screened region to a higher dose range. The acceptable dose range corresponds to acceptable breakdown voltage values for the screened region.

公开(公告)号：US20220165688A1

公开(公告)日：2022-05-26

申请号：US17103447

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L23/60 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

公开(公告)号：US20220013160A1

公开(公告)日：2022-01-13

申请号：US17448976

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Kenneth W. Marr ,  Michael A. Smith

IPC: G11C11/4078 ,  G11C11/16 ,  G11C11/22 ,  G11C7/24 ,  G11C8/20 ,  G11C16/04 ,  G11C16/22

Abstract: Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.

公开(公告)号：US20210319827A1

公开(公告)日：2021-10-14

申请号：US16846120

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Kenneth W. Marr ,  Michael A. Smith

IPC: G11C11/4078 ,  G11C16/04 ,  G11C16/22

Abstract: Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.

公开(公告)号：US11139289B2

公开(公告)日：2021-10-05

申请号：US16543724

申请日：2019-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22 ,  H01L21/28 ,  H01L21/3213 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/311

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device, as well as apparatus having such circuit-protection devices.

公开(公告)号：US10930585B2

公开(公告)日：2021-02-23

申请号：US16409464

申请日：2019-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

公开(公告)号：US10910310B2

公开(公告)日：2021-02-02

申请号：US16413470

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L21/44 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

公开(公告)号：US10580766B2

公开(公告)日：2020-03-03

申请号：US16543715

申请日：2019-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L21/28 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22 ,  H01L21/311 ,  H01L21/3213 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US10141330B1

公开(公告)日：2018-11-27

申请号：US15606415

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay ,  Michael A. Smith ,  Brett D. Lowe

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11575

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures. Semiconductor device structures, semiconductor devices, and electronic systems are also described.