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    Integrated Assemblies
    41.
    发明申请
    Integrated Assemblies 有权

    公开(公告)号：US20220352383A1

    公开(公告)日：2022-11-03

    申请号：US17864244

    申请日：2022-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Haitao Liu ,  Kamal M. Karda

    IPC: H01L29/786 ,  H01L27/11514 ,  H01L29/49 ,  H01L27/108 ,  H01L29/51

    Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

    Integrated assemblies
    42.
    发明授权
    Integrated assemblies 有权

    公开(公告)号：US11411118B2

    公开(公告)日：2022-08-09

    申请号：US17017426

    申请日：2020-09-10

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Haitao Liu ,  Kamal M. Karda

    IPC: H01L29/786 ,  H01L27/11514 ,  H01L29/49 ,  H01L27/108 ,  H01L29/51

    Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL
    44.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL 有权

    公开(公告)号：US20210272965A1

    公开(公告)日：2021-09-02

    申请号：US17146043

    申请日：2021-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/108 ,  G11C11/4097

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

    PASSING ACCESS LINE STRUCTURE IN A MEMORY DEVICE
    49.
    发明申请
    PASSING ACCESS LINE STRUCTURE IN A MEMORY DEVICE 有权
    在存储器件中通入访问线结构

    公开(公告)号：US20160104709A1

    公开(公告)日：2016-04-14

    申请号：US14511371

    申请日：2014-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

    IPC: H01L27/108 ,  G11C11/407

    CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

    Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

    Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

    VERTICAL ACCESS DEVICES, SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED METHODS
    50.
    发明申请
    VERTICAL ACCESS DEVICES, SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED METHODS 有权
    垂直存取设备，半导体器件结构和相关方法

    公开(公告)号：US20150243748A1

    公开(公告)日：2015-08-27

    申请号：US14190807

    申请日：2014-02-26

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Haitao Liu ,  Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir

    IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66666 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/7827

    Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.

    Abstract translation: 垂直存取装置包括半导体基底，其包括第一源极/漏极区域，从半导体基底垂直延伸的半导体柱和邻近半导体支柱的侧壁的栅电极。 半导体柱包括覆盖第一源极/漏极区域的沟道区域和覆盖沟道区域的第二源极/漏极区域。 半导体柱的相对的侧壁不与栅电极或另一栅电极相邻。 还描述了半导体器件结构，形成垂直访问器件的方法以及形成半导体结构的方法。

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