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公开(公告)号：US20250072118A1
公开(公告)日：2025-02-27
申请号：US18826246
申请日：2024-09-06
Applicant: Micron Technology, Inc.
Inventor： Hernan Castro , Stephen W. Russell , Stephen H. Tang
Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.
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公开(公告)号：US20240357837A1
公开(公告)日：2024-10-24
申请号：US18642555
申请日：2024-04-22
Applicant: Micron Technology, Inc.
Inventor： Darwin A. Clampitt , Stephen W. Russell , Steven P. Turini , Farrell M. Good , Kolya Yastrebenetsky , Nirav Vora , Zhao Zhao
CPC classification number: H10B63/845 , H10B63/10
Abstract: Methods, systems, and devices for contact formation for a memory device are described. A memory device manufacturing operation may include forming bit lines and word lines in a same step. In some cases, the memory device may include word line contact portions that couple respective word lines with respective word line contacts located below the word lines. For example, the word line contact portions may be located between word lines and a substrate of the memory array. In such cases, the processing step may be used for formation of word lines, bit lines, and word line contact portions. Additionally, or alternatively, the memory device manufacturing operation may include forming a sacrificial ring around bit line contacts, which may isolate bit line contacts from a nitride layer.
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公开(公告)号：US12035543B2
公开(公告)日：2024-07-09
申请号：US17064099
申请日：2020-10-06
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Stephen H. Tang , Stephen W. Russell
CPC classification number: H10B63/845 , H10B53/20 , H10B63/20 , H10B63/22 , H10B63/24 , H10B63/80 , H10B63/84 , H10N70/235 , H10N70/245
Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
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公开(公告)号：US11848048B2
公开(公告)日：2023-12-19
申请号：US17456968
申请日：2021-11-30
Applicant: Micron Technology, Inc.
Inventor： Ahmed Nayaz Noemaun , Chandra S. Danana , Durga P. Panda , Luca Laurin , Michael J. Irwin , Rekha Chithra Thomas , Sara Vigano , Stephen W. Russell , Zia A. Shafi
IPC: G11C11/00 , G11C13/00 , H01L29/423 , H10B63/00
CPC classification number: G11C13/0023 , G11C13/0004 , H01L29/4236 , H01L29/42376 , H10B63/84 , G11C2213/71
Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.
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公开(公告)号：US20230298951A1
公开(公告)日：2023-09-21
申请号：US17696261
申请日：2022-03-16
Applicant: Micron Technology, Inc.
Inventor： Chase M. Hunter , Marlon W. Hug , Stephen W. Russell , Rajesh Kamana , Amitava Majumdar , Radhakrishna Kotti , Ahmed N. Noemaun , Tejaswi K. Indukuri
IPC: H01L21/66
Abstract: Test structures for wafers are disclosed. A device may include a silicon wafer including a number of die and a scribe area between two die of the number of die. The scribe area may include one or more test structures. The test structures may include a p-doped region and an n-doped region adjacent to the p-doped region. The test structures may also include a first contact electrically coupled to the p-doped region and a second contact electrically coupled to the n-doped region. The second contact may be proximate to the first contact. Associated devices, systems, and methods are also disclosed.
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Patent Agency Ranking
公开(公告)号：US11600707B2
公开(公告)日：2023-03-07
申请号：US15930090
申请日：2020-05-12
Applicant: Micron Technology, Inc.
Inventor： Ahmed Nayaz Noemaun , Stephen W. Russell , Tao D. Nguyen , Santanu Sarkar
Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.
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公开(公告)号：US20210312978A1
公开(公告)日：2021-10-07
申请号：US17236700
申请日：2021-04-21
Applicant: Micron Technology, Inc.
Inventor： David Ross Economy , Stephen W. Russell
Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.
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公开(公告)号：US20210167127A1
公开(公告)日：2021-06-03
申请号：US17174027
申请日：2021-02-11
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Stephen H. Tang , Stephen W. Russell
IPC: H01L27/24 , H01L27/11514
Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
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公开(公告)号：US20210035612A1
公开(公告)日：2021-02-04
申请号：US17062024
申请日：2020-10-02
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Stephen W. Russell , Stephen H. Tang
IPC: G11C5/06 , H01L27/105 , G11C8/10 , H01L23/50
Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
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公开(公告)号：US20190327835A1
公开(公告)日：2019-10-24
申请号：US15961550
申请日：2018-04-24
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Stephen W. Russell , Stephen H. Tang
Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.
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