公开(公告)号：US20190287579A1

公开(公告)日：2019-09-19

申请号：US16429510

申请日：2019-06-03

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06 ,  H01L27/108 ,  H01L27/092 ,  H01L27/06 ,  H01L29/78

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

公开(公告)号：US10366738B2

公开(公告)日：2019-07-30

申请号：US15797462

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/108 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US20190019544A1

公开(公告)日：2019-01-17

申请号：US16035147

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/22

Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.

公开(公告)号：US10177159B2

公开(公告)日：2019-01-08

申请号：US15796611

申请日：2017-10-27

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Scott J. Derner

IPC: G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G11C11/419

Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

公开(公告)号：US20190006365A1

公开(公告)日：2019-01-03

申请号：US15986628

申请日：2018-05-22

Applicant: Micron Technology , Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  H01L29/08 ,  H01L49/02

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C11/403 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L28/90 ,  H01L29/0847

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US10153281B2

公开(公告)日：2018-12-11

申请号：US15664143

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore

IPC: H01L27/108 ,  H01L27/07 ,  H01L49/02 ,  H01L29/78 ,  G11C11/403 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.

公开(公告)号：US10127972B2

公开(公告)日：2018-11-13

申请号：US15679042

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4091 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C8/16 ,  G11C11/4096 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US10074414B2

公开(公告)日：2018-09-11

申请号：US15679016

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11509

CPC classification number: G11C11/2257 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H01L27/11509 ,  H01L27/11514

Abstract: Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US10043566B2

公开(公告)日：2018-08-07

申请号：US15641020

申请日：2017-07-03

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US20180218765A1

公开(公告)日：2018-08-02

申请号：US15797462

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L23/528 ,  H01L27/108 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/404 ,  G11C11/4094 ,  H01L29/78 ,  H01L49/02 ,  H01L27/02

CPC classification number: G11C11/4085 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10897 ,  H01L28/90 ,  H01L29/7827

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.