公开(公告)号：US08188535B2

公开(公告)日：2012-05-29

申请号：US12436580

申请日：2009-05-06

申请人： Yoshinobu Asami

发明人： Yoshinobu Asami

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  G11C16/0441 ,  H01L27/11521 ,  H01L27/1214 ,  H01L29/66825

摘要： An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer.

摘要翻译： 即使在重复执行写入和擦除的情况下，也是抑制读取错误的目的。 此外，另一个目的是降低写入电压和擦除电压，同时抑制存储晶体管的面积增加。 浮置栅极和控制栅极在其上方设置有用于写入操作和擦除操作的第一半导体层和设置在基板上的用于读取操作的第二半导体层之间的绝缘膜; 使用第一半导体层进行向浮栅的注入和释放电子; 并且使用第二半导体层执行读取。

公开(公告)号：US08785766B2

公开(公告)日：2014-07-22

申请号：US13161669

申请日：2011-06-16

申请人： Yoshinobu Asami ,  Tomokazu Yokoi

发明人： Yoshinobu Asami ,  Tomokazu Yokoi

IPC分类号： H01L31/06

CPC分类号： B82Y20/00 ,  B82Y10/00 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0262 ,  H01L31/035218 ,  H01L31/035236 ,  H01L31/0384 ,  H01L31/075 ,  H01L31/18 ,  Y02E10/52 ,  Y02E10/548

摘要： A novel photoelectric conversion device in which energy of light can be effectively utilized and performance can be improved is provided. A photoelectric conversion device includes a photoelectric conversion element and an energy conversion layer provided on a light-receiving side of a photoelectric conversion layer included in the photoelectric conversion element. The energy conversion layer includes a plurality of first layers and a plurality of second layers. The first layer and the second layer are alternately stacked. The thickness of the first layer is greater than or equal to 0.5 nm and less than or equal to 10 nm, and the thickness of the second layer is greater than or equal to 0.5 nm and less than or equal to 10 nm. The second layer can be formed using a material having a larger energy band gap than that of a material used for the first layer.

摘要翻译： 提供了能够有效利用光的能量并提高性能的新颖的光电转换装置。 光电转换装置包括光电转换元件和设置在包含在光电转换元件中的光电转换层的光接收侧的能量转换层。 能量转换层包括多个第一层和多个第二层。 第一层和第二层交替堆叠。 第一层的厚度大于或等于0.5nm且小于或等于10nm，第二层的厚度大于或等于0.5nm且小于或等于10nm。 可以使用具有比用于第一层的材料更大的能带隙的材料形成第二层。

公开(公告)号：US20110308568A1

公开(公告)日：2011-12-22

申请号：US13163091

申请日：2011-06-17

申请人： Yoshinobu Asami

发明人： Yoshinobu Asami

IPC分类号： H01L31/042

CPC分类号： H01L31/028 ,  H01L27/302 ,  H01L31/03682 ,  H01L31/03685 ,  H01L31/03762 ,  H01L31/0687 ,  H01L31/0725 ,  H01L31/076 ,  Y02E10/544 ,  Y02E10/545 ,  Y02E10/546 ,  Y02E10/547 ,  Y02E10/548

摘要： A photoelectric conversion device includes a first cell including a photoelectric conversion layer, a second cell over the first cell including a photoelectric conversion layer formed of a material having a wider band gap than that of the first cell, first and second electrodes under a surface of the first cell which is opposite to the second cell, and a third electrode over a surface of the second cell which is opposite to the first cell. The first and second cells each include a p-n or p-i-n junction, the first and second cells are in contact with each other and a p-n junction is formed in a contact portion therebetween, the first cell is electrically connected to the first and second electrodes to form a back contact structure, and the second cell is electrically connected to the third electrode.

摘要翻译： 光电转换装置包括：第一单元，包括光电转换层;第一单元，第二单元，包括由具有比第一单元的带隙更宽的材料形成的光电转换层;第一单元， 与第二单元相对的第一单元，以及与第一单元相对的第二单元的表面上的第三电极。 第一单元和第二单元各自包括pn或pin结，第一单元和第二单元彼此接触并且在其间的接触部分中形成pn结，第一单元电连接到第一和第二电极以形成 背接触结构，并且第二单元电连接到第三电极。

公开(公告)号：US07968932B2

公开(公告)日：2011-06-28

申请号：US11643195

申请日：2006-12-20

申请人： Yoshinobu Asami

发明人： Yoshinobu Asami

IPC分类号： H01L29/788 ,  H01L29/66

CPC分类号： H01L29/78621 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/66825 ,  H01L2029/7863

摘要： A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating-film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate-electrode, generated due to the floating gate electrode.

摘要翻译： 一种半导体器件，其以自对准的方式形成，而不会在形成控制栅电极时产生不对准的问题，并且其中不产生控制栅电极和浮栅之间的泄漏，以及半导体器件的制造方法 设备。 半导体器件包括半导体膜，半导体膜上的第一栅极绝缘膜，第一栅极绝缘膜上方的浮置栅极电极，覆盖浮置栅电极的第二栅极绝缘膜和第二栅极绝缘膜上的控制栅电极 栅极绝缘膜。 控制栅电极被形成为覆盖浮置栅极，第二栅极绝缘膜介于其间，控制栅电极设置有侧壁，并且侧壁形成在控制栅电极的台阶部分上，产生 由于浮栅电极。

公开(公告)号：US07768014B2

公开(公告)日：2010-08-03

申请号：US11337554

申请日：2006-01-24

申请人： Yoshinobu Asami

发明人： Yoshinobu Asami

IPC分类号： H01L27/108 ,  H01L29/00

CPC分类号： H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/13 ,  H01L28/91 ,  H01L29/41733 ,  H01L29/51 ,  H01L29/78618

摘要： As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention that a memory element sandwiched between electrodes has an organic compound, and an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element; therefore cost can be reduced.

摘要翻译： 对于以由RFID代表的半导体器件中实现的存储元件，本发明的目的是减少制造步骤，并提供具有降低成本的具有该元件的存储元件和存储电路。 本发明的特征在于，夹在电极之间的存储元件具有有机化合物，并且与控制存储元件的半导体元件连接的电极用作存储元件的电极。 此外，在绝缘表面上形成的非常薄的半导体膜用于存储元件; 因此可以降低成本。

公开(公告)号：US08994009B2

公开(公告)日：2015-03-31

申请号：US13602352

申请日：2012-09-04

申请人： Yoshinobu Asami ,  Riho Kataishi

发明人： Yoshinobu Asami ,  Riho Kataishi

IPC分类号： H01L51/00 ,  H01L31/0216

CPC分类号： H01L31/02167 ,  Y02E10/549

摘要： To provide a photoelectric conversion device which has little light loss caused by light absorption in a window layer, the photoelectric conversion device includes a first electrode, a first semiconductor layer formed over the first electrode, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, and a second electrode formed over the third semiconductor layer; and the first semiconductor layer is a light-transmitting semiconductor layer containing an organic compound and an inorganic compound, and the second semiconductor layer and the third semiconductor layer are each a semiconductor layer containing an organic compound.

摘要翻译： 为了提供在窗口层中由光吸收引起的光损失小的光电转换装置，光电转换装置包括第一电极，形成在第一电极上的第一半导体层，形成在第一半导体层上的第二半导体层， 形成在所述第二半导体层上的第三半导体层，以及形成在所述第三半导体层上的第二电极; 并且第一半导体层是含有有机化合物和无机化合物的透光性半导体层，第二半导体层和第三半导体层各自为含有有机化合物的半导体层。

公开(公告)号：US08252643B2

公开(公告)日：2012-08-28

申请号：US13163927

申请日：2011-06-20

申请人： Yoshinobu Asami

发明人： Yoshinobu Asami

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L29/78621 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/66825 ,  H01L2029/7863

摘要： A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate electrode, generated due to the floating gate electrode.

摘要翻译： 一种半导体器件，其以自对准的方式形成，而不会在形成控制栅电极时产生不对准的问题，并且其中不产生控制栅电极和浮栅之间的泄漏，以及半导体器件的制造方法 设备。 半导体器件包括半导体膜，半导体膜上的第一栅极绝缘膜，第一栅极绝缘膜上方的浮置栅电极，覆盖浮置栅电极的第二栅极绝缘膜，以及位于第二栅极上的控制栅电极 绝缘膜。 控制栅电极被形成为覆盖浮置栅电极，第二栅极绝缘膜插入其间，控制栅电极设置有侧壁，并且侧壁形成在控制栅电极的阶梯部分上，由此产生 到浮栅电极。

公开(公告)号：US08198666B2

公开(公告)日：2012-06-12

申请号：US12699938

申请日：2010-02-04

申请人： Yoshinobu Asami ,  Manabu Sato

发明人： Yoshinobu Asami ,  Manabu Sato

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1266

摘要： A nonvolatile memory element which is provided with a floating gate electrode and a high withstand voltage transistor which is provided with a thick gate insulating film are formed over one substrate without increase in a driving voltage of the nonvolatile memory element. A stacked film of a first insulating film and a second insulating film is formed between an island-like semiconductor region and a floating gate electrode of the nonvolatile memory element and between an island-like semiconductor region and a gate electrode of the transistor. The first insulating film overlapping with the floating gate electrode is removed, and the insulating film between the island-like semiconductor region and the floating gate electrode is formed thinner than the gate insulating film of the transistor. The transistor includes a conductive film which is formed in the same layer as the floating gate electrode and a conductive film which is formed in the same layer as a control gate electrode, and these two conductive films are electrically connected to each other and function as the gate electrodes of the transistor.

摘要翻译： 在不增加非易失性存储元件的驱动电压的情况下，在一个衬底上形成设置有浮栅电极和设置有厚栅极绝缘膜的高耐压晶体管的非易失性存储元件。 第一绝缘膜和第二绝缘膜的层叠膜形成在非易失性存储元件的岛状半导体区域和浮栅之间以及晶体管的岛状半导体区域和栅电极之间。 去除与浮栅电极重叠的第一绝缘膜，并且形成岛状半导体区域和浮置栅电极之间的绝缘膜比晶体管的栅极绝缘膜更薄。 晶体管包括形成在与浮置栅电极相同的层中的导电膜和与控制栅电极形成在同一层中的导电膜，并且这两个导电膜彼此电连接并用作 晶体管的栅电极。

公开(公告)号：US08193574B2

公开(公告)日：2012-06-05

申请号：US12434390

申请日：2009-05-01

申请人： Yoshinobu Asami

发明人： Yoshinobu Asami

IPC分类号： H01L29/788

CPC分类号： H01L27/12 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： To reduce the writing and erasing voltages of a memory transistor without increasing the area of a memory cell, and to reduce the area of a memory cell without increasing the writing and erasing voltages. The memory cell includes a memory transistor having a first island-shaped semiconductor region, a floating gate and a control gate. In addition, a second island-shaped semiconductor region is formed under the floating gate with an insulating film interposed therebetween. Since the second island-shaped semiconductor region is electrically connected to the control gate, a capacitance is formed between the second island-shaped semiconductor region and the floating gate. This capacitance contributes to an increase in the coupling ratio of the memory transistor, which makes it possible to increase the coupling ratio without increasing the area of the memory cell. Furthermore, the area of the memory cell can be reduced without reducing the coupling ratio.

摘要翻译： 为了减小存储晶体管的写入和擦除电压而不增加存储单元的面积，并且在不增加写入和擦除电压的情况下减小存储单元的面积。 存储单元包括具有第一岛状半导体区域，浮置栅极和控制栅极的存储晶体管。 此外，第二岛状半导体区域形成在浮置栅极之下，其间插入有绝缘膜。 由于第二岛状半导体区域电连接到控制栅极，所以在第二岛状半导体区域和浮置栅极之间形成电容。 该电容有助于存储晶体管的耦合比的增加，这使得可以增加耦合比而不增加存储单元的面积。 此外，可以在不降低耦合比的情况下减小存储单元的面积。

公开(公告)号：US20120118352A1

公开(公告)日：2012-05-17

申请号：US13293180

申请日：2011-11-10

申请人： Yoshinobu Asami

发明人： Yoshinobu Asami

IPC分类号： H01L31/052

CPC分类号： H01L31/0547 ,  H01L31/048 ,  Y02E10/52

摘要： A reflection member is provided for a space between photoelectric conversion cells or a periphery of the photoelectric conversion cells, which is the place not provided with the photoelectric conversion cell, so that a peak portion of the reflection member is higher than a surface of the photoelectric conversion cells. Accordingly; light having entered the space between the photoelectric conversion cells or the periphery of the photoelectric conversion cells, which does not contribute to power generation under normal circumstances, can be guided to the photoelectric conversion cell through reflection by the reflection member. Note that since the peak portion of the reflection member is higher than the surface of the photoelectric conversion cells, sunlight can be guided to the photoelectric conversion cell through one-time reflection, whereby the object can be achieved.

摘要翻译： 为光电转换单元之间的空间或光电转换单元周边设置反射构件，该反射构件是没有设置光电转换单元的位置，使得反射构件的峰值部分高于光电转换单元的表面 转换单元格。 相应地 可以通过反射构件的反射将已经进入光电转换单元之间的空间或光电转换单元的外围的光在正常情况下对发电无贡献的光线引导到光电转换单元。 注意，由于反射构件的峰值部分高于光电转换单元的表面，所以可以通过一次反射将太阳光引导到光电转换单元，从而可以实现对象。